Opinion for the court filed by Circuit Judge DYK. Dissenting opinion filed by Circuit Judge NEWMAN.'
Opinion for the court filed by Circuit Judge DYK.
Synopsys, Inc. (“Synopsys”), the petitioner, appeals a final decision of the Patent Trial and Appeal Board (“Board”) in an inter partes review of claims of U.S. Patent No. 6,240,376 (“the '376 patent”). Mentor Graphics Corporation (“Mentor”), the patent owner, cross appeals. The Board found that claims 5, 8, and 9 were invalid as anticipated (which Mentor does not challenge on appeal) but declined to find that claims 1 and 28 were anticipated (which Synopsys appeals). We conclude that the Board did not err in its ruling that claims 1 and 28 were not invalid. We also hold that (1) the final order of the Board need not address every claim raised in the petition for review, and (2) the Board did not err in denying Mentor’s motion to amend. Accordingly, we affirm.
Background
The '376 patent claims a method of tracing bugs, ie., errors in coding, in the de[1312]*1312sign of computer chips. An error in the design of a computer chip, even a minor one, can be extremely problematic and costly for the company that produces the chip. Thus, before a chip is manufactured, the design undergoes significant testing to make sure that the chip performs as intended. The '376 patent relates to a method of testing involving a software or hardware simulation of the chip. The method allows a chip designer to trace errors discovered during testing back to the original source code that a designer uses to program the chip so that these errors can be corrected.
To explain the specifics of this invention, some background information about chip design is necessary. Chip designers write source code to design the basic operation of the circuits that make up a computer chip. For example, a chip designer may indicate that a particular “gate” — or component of the circuit — is supposed to provide a particular output given a particular input. The source code indicates this using general logical statements, such as “if A=0, then B=0, else B=l.”1 See, e.g., '376 patent, fig. 4. However, this source code must be “translated” into the actual design of the chip. Specialized software “synthesizes,” ie., translates, the source code into a “gate-level netlist,” or a basic schematic of the chip. Id. at 1:26-36. But the design still may be incomplete, as it may contain redundant circuitry based on a direct translation from the source code. Yet another specialized piece of software is then used to optimize the design, which removes the superfluous components from the circuit and results in a simpler and more efficient circuit without losing any functionality.2
When the design process is complete, chip designers use specialized software or hardware to imitate the behavior of the final circuitry to test whether the chip does what it is supposed to do. For example, a designer can simulate the circuit from the original source code. During this test, if there is a problem, the designer can fix it by going back to the code and making modifications. However, it is often difficult to trace back errors to the right place in the source code because high level information in the source code is lost during translation and optimization. The loss of this information makes identifying and correcting errors much more costly and time consuming. The '376 patent seeks to solve this problem. The invention uses “instrumented signals” to identify the place in the source code where the error resides, thus allowing the designer to go back to the specific part of the source code to correct the error. '376 patent, col. 2 11. 40-43.
On September 26, 2012, Synopsys filed a petition for inter partes review of claims 1-15 and claims 20-33 of the '376 patent, alleging that these claims were anticipated or would have been obvious in light of various prior art references, including U.S. Patent No. 6,132,109 (“Gregory”). In its preliminary patent owner response, Mentor contested Synopsys’s invalidity contentions and also argued that Synop-[1313]*1313sys’s petition was time-barred and moved for discovery relating to the time-bar. Specifically, after filing the petition for inter partes review, Synopsys had acquired an entity who had previously been sued by Mentor for infringement of the '376 patent more than one year earlier. Mentor argued that the petition for inter partes review was time-barred under 35 U.S.C. § 315(b), which states that “[a]n inter partes review may not be instituted if the petition requesting the proceeding is filed more than 1 year after the date on which the petitioner, real party in interest, or privy of the petitioner is served with a complaint alleging infringement of the patent.” In the alternative, Mentor argued that the acquired entity, rather than Sy-nopsys, was the appropriate real party in interest to the inter partes review and, in light of the earlier suit, the inter partes review was time barred.
On February 22, 2013, the Board instituted review of claims 1-9, 11, and 28-29 based solely on anticipation by Gregory, finding that the petition “show[ed] that there is a reasonable likelihood that the petition would prevail” in demonstrating unpatentability. 35 U.S.C. § 314(a). The Board denied the petition with respect to claims 10, 12-15, 20-27, and 30-33, finding that there was no reasonable likelihood of invalidity because Synopsys had not shown, for example, how any prior art disclosed “local variable assignment state-mentfs]” as required by claim 20. J.A. 34-35.
In the decision to institute, the Board also rejected Mentor’s argument that Sy-nopsys’s petition was time-barred by section 315(b) of title 35. The Board found that the § 315(b) bar is measured as of the filing date of the petition, pursuant to its regulation interpreting this section, 37 C.F.R. § 42.101(b), which states that a petition is barred only if “[t]he petition requesting the proceeding is filed more than one year after the date on which the petitioner ... is served with a complaint alleging infringement of the patent.” According to the Board, Mentor had not “provide[d] persuasive evidence that Synopsis [sic] and [the newly acquired entity that had been sued by Mentor more than one year earlier] were in privity on the filing date of the petition.” J.A. 16. The Board also found that Synopsys was the appropriate real party in interest. Therefore, the Board found that the petition was not time barred.
After institution, Mentor filed a motion to amend and substitute claims 34-43 for claims 1, 5, 28, 2, 3, 6, 8, 9, 11, and 29, respectively, which was opposed by Synop-sys.
After an oral hearing, the Board issued its final written decision on February 19, 2014. Synopsys Inc. v. Mentor Graphics Corp., IPR2012-00042, 2014 WL 722009, Paper 60 (PTAB February 19, 2014) (“Bd. Op”). The Board found claims 5, 8, and 9 anticipated by Gregory. However, the Board also found that claims 1-4, 6, 7, 11, 28, and 29 were not anticipated. In addition, the Board denied Mentor’s motion to substitute claims 35, 40, and 41 for claims 5, 8, and 9. According to the Board, Mentor failed to “demonstrate general patenta-bility over prior art,” including Gregory. Id. at 47. “As the moving party,” Mentor bore “the burden to show entitlement to the relief requested,” namely the amendment of claims. Id.
Synopsys appeals, arguing that the Board erred in finding claims 1 and 28 not anticipated and by issuing a final decision that did not address the validity of all [1314]*1314cl a im a raised in the petition. Mentor cross appeals, challenging the Board’s finding that the petition was not time barred and the Board’s denial of its motion to amend. The PTO has intervened as an interested party to defend its procedures. We have jurisdiction under 28 U.S.C. § 1295(a)(4)(A). We review the Board’s factual findings for substantial evidence and its legal conclusions de novo. In re Baxter Int’l, Inc., 678 F.3d 1357, 1361 (Fed.Cir.2012).
Discussion
I
Synopsys first contends that the final decision of the Board erroneously failed to address every claim raised in the petition for inter partes review. As we have previously explained, inter partes review proceeds in two stages. See St. Jude Med., Cardiology Div., Inc. v. Volcano Corp., 749 F.3d 1373, 1375 (Fed.Cir.2014). In the first stage, the Board, acting on behalf of the Director, reviews the petition for inter partes review and any patent owner preliminary response to decide whether “there is a reasonable likelihood that the petitioner would prevail with respect to at least 1 of the claims challenged in the petition.” 35 U.S.C. § 314(a); 37 C.F.R. § 42.4(a). The PTO has adopted a regulation allowing the Board to initiate inter partes review “on all or some of the challenged claims.” 37 C.F.R. § 42.108(a). At the second stage, the Board conducts the inter partes review and then issues a final decision with respect to “any patent claim challenged by the petitioner.” 35 U.S.C. § 318(a).3
The decision of the Board to institute inter partes review cannot be appealed. 35 U.S.C. § 314(d); In re Cuozzo Speed Techs., LLC, 793 F.3d 1268, 1273 (Fed.Cir.2015), cert. granted, No. 15-446, — U.S. —, 136 S.Ct. 890, 890, 193 L.Ed.2d 783, 2016 WL 205946, at *1.4 The PTO argues that the “logical import” of Synopsys’s challenge is a challenge to the decision to institute. Br. of PTO, at 15-16. However, Synopsys does not challenge the decision to institute but rather the scope of the final decision itself. Because Synopsys challenges the final decision, we can hear this appeal. The statute allows “[a] party dissatisfied with the final written decision of the Patent Trial and Appeal Board” to “appeal the decision.” 35 U.S.C. § 319; Versata Dev. Grp., Inc. v. SAP Am., Inc., 793 F.3d 1306, 1322 (Fed.Cir.2015).
On the merits, Synopsys argues that, because § 318(a) directs the Board to issue a final written decision with respect to “any patent claim challenged by the petitioner,” the Board’s final decision must address every claim raised in the petition.5 However, the statute cannot be read to [1315]*1315impose such a requirement. First, the text makes clear that the claims that the Board must address in the final decision are different than the claims raised in the petition. Congress explicitly chose to use a different phrase when describing claims raised in the petition for inter partes review in § 314(a) and claims on which inter partes review has been instituted in § 318(a). Section 314(a) specifies that Board may not institute inter partes review unless “the information presented in the petition ... and any response filed ... shows that there is a reasonable likelihood that the petitioner would prevail with respect to at least 1 of the claims challenged in the petition.” 35 U.S.C. § 314(a) (emphasis added). However, in describing the final written decision, Congress stated that the Board must issue a final written decision with respect to any “claim challenged by the petitioner.” 35 U.S.C. § 318(a) (emphasis added). When Congress chooses to use two different words or phrases, this typically suggests that the two were deemed to have two different meanings. See, e.g., Bailey v. United States, 516 U.S. 137, 146, 116 S.Ct. 501, 133 L.Ed.2d 472 (1995) (distinction between “used” and “intended to be used” creates implication that a related provision’s reliance on “use” alone refers to actual and not intended use”).
In addition, the conditional phrase “[i]f an inter partes review is instituted” in § 318(a) also strongly suggests that the “challenged” claims referenced are the claims for which inter partes review was instituted, not every claim challenged in the petition. Thus, the text of § 318(a) demonstrates that the Board need only issue a final written decision with respect to claims on which inter partes review has been initiated and which are challenged by the petitioner after the institution stage.
Second, the statute would make very little sense if it required the Board to issue final decisions addressing patent claims for which inter partes review had not been initiated, as Synopsys admitted at oral argument. After inter partes review is initiated, the patent owner files a full response to the petition. See 35 U.S.C. § 316(a)(8); 37 C.F.R. § 42.120. In addition, both parties may submit information to supplement the record by taking discovery, submitting affidavits, and by submitting expert declarations. See 37 C.F.R. §§ 42.123, 42.51, 42.65. Parties may present their cases to the Board in an oral hearing. 37 C.F.R. § 42.70. All of these various mechanisms allow the Board to issue a final decision based on a full record rather than just on the limited record in the initial petition and the patent owner’s preliminary response. See 35 U.S.C. § 314(a) (specifying that the decision to institute is made on “information presented in the petition ... and any [preliminary] response” filed by the patent owner). It would make no sense to interpret § 318 in a way that would require the Board to issue a final determination on validity of patent claims without the benefit of this additional argument and record.
At the same time, the statute is quite clear that the PTO can choose whether to institute inter partes review on a claim-by-claim basis. In deciding when to institute IPR, the statute requires a claim-by-claim inquiry to determine whether “there is a reasonable likelihood that the petitioner would prevail with respect to at least 1 of the claims challenged in the petition.” 35 U.S.C. § 314(a) (emphasis added). Unless at least one of the claims satisfies this inquiry, the Board cannot institute. The [1316]*1316statute strongly implies that the initiation decision be made on a claim-by-claim basis and that the Board can pick and choose among the claims in the decision to institute. In fact, nothing in § 314 requires institution of inter partes review under any circumstance.
Although we find that the language is clear, if there were any doubt about the Board’s authority and the statute were deemed ambiguous, the PTO has promulgated a regulation allowing the Board to institute as to some or all of the claims. The regulation “authorize[s] the review to proceed on all or some of the challenged claims and on all or some of the grounds of unpatentability asserted for each claim.” 37 C.F.R. § 42.108. Contrary to Synop-sys’s argument that this regulation is invalid, the PTO has explicit authority to promulgate regulations “setting forth the standards for the showing of sufficient grounds to institute” inter partes review. 35 U.S.C. § 316(a)(2). This regulation is plainly an exercise of that authority. Under Chevron U.S.A., Inc. v. Natural Resources Defense Council, Inc., 467 U.S. 837, 104 S.Ct. 2778, 81 L.Ed.2d 694 (1984), this regulation is a reasonable interpretation of the statutory provision governing the institution of inter partes review. See Cuozzo, 793 F.3d at 1278. As the PTO noted in adopting the regulation, the claim-by-claim approach “streamline[s] and con-vergéis] the issues for consideration” and “aids in the efficient operation of the Office and the ability of the Office to complete the [review] within the one-year time-frame.” Changes to Implement Inter Partes Review Proceedings, Post-Grant Review Proceedings, and Transitional Program for Covered Business Method Patents, 77 Fed.Reg. 48703 (Aug. 14, 2012) (Response to Comment 60).
Synopsys also argues that the legislative history and the structure of the AIA support its construction. For this assertion, it points to a few floor statements suggesting that inter partes review “will completely substitute for at least the patents-and-printed publication portion of’ infringement litigation. 157 Cong. Rec. S1376 (daily ed. Mar. 8, 2011) (statement of Sen. Kyl); see also 154 Cong. Rec. S9989 (daily ed. Sept. 27, 2008) (statement of Sen. Kyl); 153 Cong. Rec. H10280 (Sept. 7, 2007) (statement of Rep. Jackson-Lee). Floor statements by a few members of the legislative branch cannot supplant the text of the bill as enacted. In addition, Synopsys argues that the Board’s practice of issuing final decisions only addressing some of the claims in the petition is inconsistent with the estoppel provisions of the AIA because final decisions that do not address all of the claims “will have limited estoppel effect” and thus do not “force a party to bring all of its claims in one forum.” Appellant’s Br. 74 (internal quotation marks omitted). The validity of claims for which the Board did not institute inter partes review can still be litigated in district court. We see no inconsistency in this. Inter partes review cannot replace the district court in all instances, for example, when claims are challenged in district court as invalid based on the on-sale bar, for claiming patent-ineligible subject matter, or on grounds of indefiniteness. See 35 "U.S.C. § 311(b) (limiting inter partes review to grounds “that could be raised under section 102 [anticipation] or 103 [obviousness] and only on the basis of prior art consisting of patents or printed publications”).6
In summary, we find no statutory requirement that the Board’s final decision [1317]*1317address every claim raised in a petition for inter partes review. Section 318(a) only requires the Board to address claims as to which review was granted.
II
We now turn to the substance of the Board’s anticipation finding with respect to claims 1 and 28. Anticipation is a question of fact. See In re Graves, 69 F.3d 1147, 1151 (Fed.Cir.1995). This court reviews the Board’s decision for substantial evidence. Dickinson v. Zurko, 527 U.S. 150, 152, 119 S.Ct. 1816, 144 L.Ed.2d 143 (1999); In re Gartside, 203 F.3d 1305, 1313 (Fed.Cir.2000).
Claims 1 and 28 read:
1. A method comprising the steps of:
a) identifying at least one statement within a register transfer level (RTL) synthesizable source code; and
b) synthesizing the source code into a gate-level netlist including at least one instrumentation signal, wherein the instrumentation signal is indicative of an execution status of the at least one statement.
28. A storage medium having stored therein processor executable instructions for generating a gate-level design from a register transfer level (RTL) synthesizable source code, wherein when executed the instructions enable the processor to synthesize the source code into a gate-level netlist including at least one instrumentation signal, wherein the instrumentation signal is indicative of an execution status of at least one synthe-sizable statement of the code.
'376 patent col. 15 ll.1-8, col. 171.62-col. 18 1.7. The Board found that Gregory disclosed everything in these claims except for “instrumentation signals” that are “indicative of an execution status of the at least one statement.” Bd. Op. at 30. The finding that the prior art disclosed all other aspects of the claims is not challenged oh appeal by the patentee. The Board construed “instrumentation signal” to be “an output signal created during synthesis of [] source code by inserting additional code into a program that indicates whether the corresponding [] source code statement is active.” Id. at 26-27. The Board construed the term “execution status” to mean “information regarding whether a particular [source code] instruction has been performed.” Id. at 27. These constructions are not challenged on appeal by the petitioner.
Rather, the petitioner asserts that Gregory discloses the “execution status” limitation. As discussed above, the '376 patent is directed to locating errors in the source code. Testing of chips is done by inputting “millions or billions of test vectors” into the chip and comparing the outputs the chip gives with expected results. '376 patent col. 4 ll. 58-60. As a very simplified example, a designer may ask the chip to compute “1 +1.” If the chip outputs 3 instead of the expected result, the de[1318]*1318signer knows that there is an error in the source code somewhere leading to that inaccurate output. When one of the tests gives an incorrect output, the designer must go back to the source code to find the error that caused this. The difficulty lies in finding the particular statement in the source code that caused the error.
During typical testing of code, programmers have access to a number of tools that help locate errors in source code. For example, programmers are able to set a “break point,” which is a signal that tells the debugging software to temporarily suspend execution of the code. '376 patent, col. 1 l.49. In other words, a programmer will artificially stop the execution of the code at a particular point and examine the results of the execution up to that point. Setting a breakpoint allows a programmer to examine only a small subset of the code and thus simplify the task of finding where in the source code errors arise by narrowing the code tested to only a portion of the entire code. Another traditional debugging method is a visual trace where a programmer can examine exactly which lines of code have been executed during one of the tests. However, “the designer typically cannot set a breakpoint from the source code during gate-level simulation” because the designs after translation “include[ ] none of the high-level information available in the ... source code.” '376 patent, col. 2 ll.5-6; col. 4 l.66-66. Thus, traditional debugging tools “such as setting breakpoints or analyzing the source code coverage are not available” when doing “gate-level” testing of the designs of chips. Id. at col. 4 l.67-col. 51.2.
The invention of the '376 patent uses instrumentation signals to “facilitate source code analysis, breakpoint debugging, and visual tracing of the source code execution path during gate-level simulation.” '376 patent, col. 2 ll. 52-55. These instrumentation signals are created in the source code as illustrated below:
[[Image here]]
[1319]*1319'376 patent, excerpts from figs. 6A and 6B.
As seen in the figure, instrumentation logic — the “trace” variables — are interspersed with the logic statements that outline the functions of the chip — the “if,” “then,” and “else” statements. Each line of code is associated with a particular instrumentation variable, which has an initial value of 0 (see 620, which initializes these variables to have a value of 0). When that fine of code is executed, the code sets that trace variable to have a value of 1 (see, e.g., 630, 632, etc., which are lines of code changing the value of the variables to 1). So, for example, if the condition in an “if’ statement above is true, the “then” part of the code will execute and the “else” part of the code will not execute. A designer can know this because the “trace” variables associated with the executed lines of code will have a value of 1 whereas the “trace” variables associated with the unexecuted lines of code will still have a value of O.
This instrumentation logic is preserved during translation, and becomes instrumentation signals in the schematic used for testing (a signal being output is the same as the variable being set to 1). Thus, chip designers can set a breakpoint by telling the testing software to stop when a particular instrumentation signal is output (ie. when a particular line of code is executed) and can visually trace the execution of the code in any given test by looking at a list of outputted instrumentation signals associated with that test.
Gregory also deals with tracing errors in chip design to source code, but uses a different method, as is uncontested. The designer, using the invention described in Gregory, can identify the “source code in the places that the designer wants to be able to debug,” and isolate those particular portions of the chip design for testing. Gregory, col. 8 1.24. During synthesis of the source code into the schematic of the chip, “the translator ... adds additional information or components to the initial circuit that indicate that certain components should not be replaced during optimization.” Gregory, col. 8, ll. 27-31. The designer then can test only those portions of the chip and, after errors are discovered, only have a smaller subset of the code to search for errors. Further,.because the code in those portions is unoptimized, it corresponds to the source code directly so if an erroneous answer is output, the designer can know exactly which lines of the original source code were executed and can narrow down even further the source of the error.
Synopsys argues that the Board erred in concluding that Gregory does not disclose instrumentation signals that are indicative of the execution status.
First, Synopsys argues that the Board applied the wrong legal standard by requiring explicit disclosure in Gregory of the “execution status” element of claims 1 and 28. According to Synopsys, Gregory implicitly or inherently discloses the “execution status.”
Synopsys relies on one sentence out of the Board decision and takes it out of context. The Board stated: “Gregory does not state explicitly that ‘tempout,’ or any other element, indicates an ‘execution status’ of an HDL instruction.” Bd. Op. at 32. However, the Board then immediately went on to discuss how Gregory does not implicitly disclose the necessary limitation. See id. The Board relied on Mentor’s expert testimony that Gregory did not disclose instrumentation signals indicative of execution status. This expert testimony does not rely on explicit disclosures’ being missing from the Gregory reference — rath[1320]*1320er, it carefully explains how the Gregory reference does not inherently (or even implicitly) disclose the necessary claim limitation. The Board did not require explicit disclosure in Gregory.
Second, Synopsys argues that the Board improperly required it to present expert testimony. For this proposition, it again points to a single sentence in the Board’s opinion where the Board stated, in weighing the quality of evidence presented by Synopsys, “Synopsys, however, does not point to any expert testimony to support these statements.” Bd. Op. at 31. Synop-sys argues that because the Board is constituted to evaluate technical arguments about technical materials, expert testimony should not be required.
We have previously found that, in the context of district court litigation, “expert testimony is not required when the references and the invention are easily understandable.” Wyers v. Master Lock Co., 616 F.3d 1231, 1242 (Fed.Cir.2010). However, when the technology is complex and “beyond the comprehension of laypersons,” expert testimony is “sometimes essential.” Centricut, LLC v. Esab Grp., Inc., 390 F.3d 1361, 1369 (Fed.Cir.2004). In the context of inter partes reviews, “Board members, because of expertise, may more often find it easier to understand and soundly explain the teachings and suggestions of prior art without expert assistance,” but “[w]hat the Board can find without an expert depends on the prior art involved in a particular case.” Belden Inc. v. Berk-Tek LLC, 805 F.3d 1064, 1079 (Fed.Cir.2015). Certainly, “[n]o rule requires a Petition to be accompanied by any declaration, let alone one from an expert guiding the Board as to how it should read prior art.” Id. At the same time, the Board is not precluded from finding that the technology in a particular case is sufficiently complex that expert testimony is essential for a petitioner to meet his burden of proving unpatentability. In this particular case, the technology involved is highly complex. The invention of the '376 patent deals with testing the design of microchips, a process that even Synopsys describes as an “extremely complicated task.” See Appellant’s Br. 6.
But we need not decide whether the Board here correctly required expert testimony. The Board here did not, in fact, require expert testimony. The Board simply noted that Mentor provided expert testimony whereas Synopsys did not, which the Board gave “substantial weight.” Bd. Op. at 31. We see no error in this approach.
Third, Synopsys argues that that the “tempout” signal of Figure 9 in Gregory is an “instrumentation signal” “indicative of an execution status.” Figure 9 “shows a circuit that a translator could produce” from source code modified as described in Gregory. Gregory, col. 12 ll. 62-63. The figure contains an output termed “temp-out” which is created from a designer’s addition of lines of code in the source code for the purposes of testing, much like the “trace” variables of the '376 patent. The Board found that “tempout” is an “instrumentation signal,” as it, like the instrumentation signals in the '376 patent, is created by adding extra source code solely for testing purposes and unrelated to the underlying functions of the chip. See Bd. Op. at 30-32. However, the Board found that this signal was not indicative of an execution status.
Synopsys argues that this finding of the Board is not supported by substantial evidence because a designer can “anaylz[e] the value of ‘tempout [ ]’ [and can] deter[1321]*1321mine a broad range of information” including whether particular line of source code has been executed. Appellant’s Br. 59. Though this “tempout” signal is typically used for a different kind of testing, see Gregory col. 13 ll. 16-29, Synopsys argues that a designer might be able to re-trace the logical steps that led to this particular output and thus can glean whether particular lines of code had been executed.
The Board gave “significant weight to the testimony of Mentor Graphics’s expert,” Bd. Op. at 28, who testified “the result of the ‘tempout’ signal is not indicative of the execution status,” id. at 31. Specifically, Mentor’s expert testified that, in several instances, knowing the temporary output “provides no information as to whether the statement is executed.” J.A. 1905. We see no error in the Board’s reliance on expert testimony to resolve this factual dispute.
Even if we were to accept Synop-sys’s assertion that “tempout” “can indicate which statement was executed,” Appellant’s Br. at 59 (emphasis added), a signal that may, under some circumstances, indicate an execution status does not meet the limitation in this case. The point'of the invention is to enable designers to more easily debug the source code based on testing of the optimized circuits. Developers could not do this if the instrumentation signal were indicative of execution status only some of the time. Thus, accordingly, the Board construed “execution status” as “information regarding whether a particular [source code] instruction has been performed,” pointing specifically to a passage in the '376 patent discussing determining “the execution status of every branch” of code. Bd. Op. at 27. In the case of this invention, partially accurate information is tantamount to no information. “The mere fact that a certain thing may result from a given set of circumstances is not sufficient” to show anticipation where’ the claim, as here, requires more. See In re Oelrich, 666 F.2d 578, 581 (C.C.P.A.1981); see also MEHL/Biophile Int’l Corp. v. Milgraum, 192 F.3d 1362, 1365 (Fed.Cir.1999) (noting that a “possibility” that under certain circumstances a laser designed for tattoo removal may be pointed at hair follicles “does not legally suffice to show anticipation” of a patent involving laser hair removal). The Board’s finding of non-anticipation in this respect is supported by substantial evidence.
Fourth, Synopsys argues that the output of logic gate 232 in Figure 9 (see figure above) meets the “execution status” limitation. As previously discussed, a logic gate is a visual representation of a particular logical statement in the source code and performs an operation based on that logic. Logic gate 232 is an “AND” gate, which means that it outputs a signal only when it receives both inputs. Synopsys argues that if a designer knew the output of this particular gate, the designer would be able to figure out whether the particular line of source code associated with that gate had been executed. The Board rejected the argument as waived because “the argument [was] presented for the first time in Synopsys’s reply and is not responsive to arguments made in Mentor Graphic’s response.” Bd. Op. at 33.
We see no error in the Board’s determination that this argument was not properly raised in the petition for inter partes review. See 37 C.F.R. § 42.23(b). In any case, the Board did not entirely ignore this argument, noting that “Synopsys does not point to any evidence or persuasive argument to explain how [the output of AND gate 232] disclose[s] the claimed instru[1322]*1322mentation signal.” Bd. Op. at 33. Substantial evidence supports the conclusion that the output of the “AND” gate is not an instrumented “output signal” as required by the undisputed claim construction of “instrumentation signal.” See Bd. Op. at 26-27 (requiring that an instrumentation signal “at least includes an output signal created during synthesis of RTL source code by inserting additional code into a program that indicates whether the corresponding [] source code statement is active ”) (emphases added).
Lastly, Synopsys argues that the “temp-out” signals of Figures 16 and 18 of Gregory disclose instrumentation signals indicative of execution status, and that the Board improperly did not address this argument in its decision.
In general, an agency issuing an order from a formal adjudication must “include a statement of findings and conclusions, and the reasons or basis therefor, on all the material issues of fact, law, or discretion presented on the record.” 5 U.S.C. § 557(c)(3)(A). This means that agencies must articulate “logical and rational” reasons for their decisions. See Allentown Mack Sales and Serv., Inc. v. NLRB, 522 U.S. 359, 374, 118 S.Ct. 818, 139 L.Ed.2d 797 (1998). However, this does not require an agency to address every argument raised by a party or explain every possible reason supporting its conclusion. See, e.g., Human Dev. Ass’n v. NLRB, 937 F.2d 657, 669 (D.C.Cir.1991) (“Although ‘the better practice’ ... might have been to identify and ... brush off the argument [that the appellant argued the agency should have addressed], the ruling under review leaves no room for doubt that the” agency decided the issue.); Am. President Lines v. NLRB, 340 F.2d 490, 492 (9th Cir.1965) (finding that, despite not making “separate rulings on each” claim, “[t]he [agency] sufficiently informed petitioner of the disposition of all of its” claims). The agency’s decision must allow effective judicial review, which means that the agency is obligated to “provide an administrative record showing the evidence on which the findings are based, accompanied by the agency’s reasoning in reaching its conclusions.” In re Sang Su Lee, 277 F.3d 1338, 1342 (Fed.Cir.2002); see also SEC v. Chenery Corp., 318 U.S. 80, 94, 63 S.Ct. 454, 87 L.Ed. 626 (1943) (“[T]he orderly functioning of the' process of review requires that the grounds upon which the administrative agency acted [are] clearly disclosed and adequately sustained”) (emphasis added).
In its final decision, the Board addressed why a “tempout” signal is not “indicative of an execution, status.” Bd. Op. at 31-32. The Board need not specifically reference Figure 18 in its finding — it only need explain itself sufficiently to allow effective judicial review.' And the Board did so here. It specifically stated that it relied on Mentor’s expert witness who gave testimony that the “tempout” signal of Figure 9 was not “indicative of execution status.” Id. The “tempout” signal of Figure 18 is the same type of signal as the “tempout” signal in Figure 9 and the arguments for why it discloses (and does not disclose) are, in essence, the same. Compare Gregory col. 13 ll. 1-6 with col. 14 ll. 27-29. Because the Board addressed whether the “tempout” signal, in general, was indicative of execution status, we find no error in the Board not having specifically referenced Figures 16 or 18 in its decision.
Ill
We next address the issues raised by the cross appeal. Mentor does not chai-[1323]*1323lenge the substance of the Board’s anticipation finding. Rather, Mentor first argues that the Board improperly instituted review because Synopsys’s petition was time barred under § 315(b). The theory is that Synopsys’s acquisition of an entity who had been sued by Mentor alleging infringement of this patent more than one year earlier should bar Synopsys from petitioning for inter partes review or, alternatively, that the acquired entity is the real party in interest, also barring the petition. See 35 U.S.C. § 315(b). At oral argument, Mentor conceded that our previous decision Achates, 803 F.3d at 658, held that the PTO’s decisions concerning the § 315(b) time bar, including determinations of the real party in interest and rulings on discovery related to such determinations, are non-appealable. Mentor agrees that Achates precludes review of this issue here. This issue is not appeal-able pursuant to § 314(d).
Mentor also argues that the Board impermissibly placed the burden of proving patentability of the proposed claims on Mentor when it denied Mentor’s contingent motion to substitute claims 35, 40, and 41 for claims 5, 8, and 9. The Board denied the motion to substitute the claims on two grounds. First, the Board found that “Mentor Graphics has not met its burden to show that independent claim 35 or claims 40 and 41, which depend from claim 35, would not have been obvious to a person of ordinary skill in the art based on the disclosure of Gregory.” Bd. Op. at 47. The Board, alternatively, found that Mentor had not shown general patentability over the prior art.
We have previously held in Microsoft Corp. v. Proxyconn, Inc. that the Board may properly place the burden of proving patentability of substitute claims on the patentee for the prior art of record. 789 F.3d 1292, 1303-08 (Fed.Cir.2015); see also Prolitec, Inc. v. ScentAir Techs., Inc., 807 F.3d 1353, 1363 (Fed.Cir.2015) (finding that “the PTO’s approach [requiring the patentee to prove patentability over the relevant prior art in the prosecution history] is a reasonable one at least in a case ... in which the Board’s denial of the motion to amend rested on a merits assessment of the entire record developed on the motion, not just on the initial motion itself’). Mentor argues that Proxyconn does not control because the Proxyconn opinion did not address whether the paten-tee ought to bear the burden to distinguish all prior art known to the patent owner and whether this requirement is contrary to 35 U.S.C. § 316(e), which states that in an inter partes review, “the petitioner shall have the burden of proving a proposition of unpatentability.”
In the present case, the Board found that Mentor “ha[d] not met its burden to show that independent claim 35 or claims 40 and 41, which depend from claim 35, would not have been obvious to a person of ordinary skill in the art based on the disclosure of Gregory.” Bd. Op. at 47. As in Proxyconn and Prolitec, we see no error in placing the burden of demonstrating patentability of substitute claims on the patentee over Gregory, which was the only piece of prior art for the inter partes review. While the Board also concluded that Mentor had not “demonstrate^] general patentability over prior art,” id., we find that the Board’s narrower holding requiring Mentor to prove patentability over Gregory sufficient to sustain the decision.
Section 316(e) does not alter, our analysis. That section reads: “In an inter partes review instituted under this chapter, the petitioner shall have the burden of [1324]*1324proving a proposition of unpatentability by a preponderance of the evidence.” 35 U.S.C. § 316(e). The introductory phrase referring to an “inter partes review instituted under this chapter” makes clear that this provision specifically relates to claims for which inter partes review was initiated, ie., the original claims of the patent that a party has challenged in a petition for review. Inter partes review was not initiated for the claims put forward in the motion to amend.
We find that Mentor’s arguments here are foreclosed by Proxyconn and Prolitec and affirm the Board’s denial of the motion to amend.7
AFFIRMED
Costs
Costs to neither party.