Synopsys, Inc. v. Mentor Graphics Corp.

78 F. Supp. 3d 958, 2015 U.S. Dist. LEXIS 6333, 2015 WL 269116
CourtDistrict Court, N.D. California
DecidedJanuary 20, 2015
DocketNo. C 12-6467 MMC
StatusPublished
Cited by5 cases

This text of 78 F. Supp. 3d 958 (Synopsys, Inc. v. Mentor Graphics Corp.) is published on Counsel Stack Legal Research, covering District Court, N.D. California primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Synopsys, Inc. v. Mentor Graphics Corp., 78 F. Supp. 3d 958, 2015 U.S. Dist. LEXIS 6333, 2015 WL 269116 (N.D. Cal. 2015).

Opinion

ORDER ON MOTIONS FOR SUMMARY JUDGMENT

MAXINE M. CHESNEY, United States District Judge

Before the Court are cross-motions for summary judgment, filed October 3, 2014, by plaintiff Synopsys Inc. (“Synopsys”) and defendant Mentor Graphics Corporation (“Mentor”), by which the parties set forth their respective positions as to the patent eligibility of eight claims as recited in three patents held by Synopsys,1 specifically, claims 1, 2, 8, and 9 of U.S. Patent No. 5,748,488 (“’488 patent”), claim 1 of U.S. Patent No. 5,530,841 (“ ’841 patent”), and claims 32, 35, and 36 of U.S. Patent No. 5,680,318 (“ ’318 patent”).2

BACKGROUND3

The three patents at issue (hereinafter “the Gregory patents”) relate generally to the field of integrated circuit (“IC” or “chip”) design. ICs are composed of logic circuits and memory circuits, which themselves are composed of “tens, hundreds, or even potentially thousands, of transistors, resistors, capacitors, or other hardware components.” (See Decl. of Ronald D. Blanton, Ph.D. (“Blanton Deck”), filed October 3, 2014, ¶ 8.) In the 1950s, when ICs were first developed, engineers would hand draw the chip designs with symbols or schematics representing the hardware components to be used. In the mid-1980s, a method of automating chip design, EDA, was developed to help solve the problem of the ever-increasing number of hardware components capable of being integrated on a chip. EDA “involves the use of computers to, among other things, create integrated circuit designs, simulate the designs using only software, and emulate the designs using a combination of hardware and software.” (Id. ¶ 14.)

The Gregory patents are directed to a form of EDA known as “logic synthesis.” In the subject field, logic synthesis is generally understood to mean the process of “using a computer tool to interpret or ‘synthesize’ a human designer’s descriptions of the operations of the integrated circuit” and then “generating],” typically as a “netlist,” the “electronic circuit components (e.g., logic circuits) ... that perform those operations.” (See id. ¶ 15.) The human-generated descriptions are written by an engineer, or “user,” in a hardware description language (HDL), one of several languages developed specifically for EDA. (Id. at ¶ 16.)

The Gregory patents claim a way of performing synthesis, described therein as “[a] method and system ... for generating a logic network using a hardware indepen[961]*961dent description means.” See ’841 patent, Abstract. Prior to the issuance of the Gregory patents, chip design required “detailed logic knowledge for most practical circuits.” Id., col. 2:9-10. In particular, for more complex circuit elements, such as “high impedance drivers, level sensitive latches and edge sensitive flip-flops,” the designer, using HDL, was required to specify the circuit element and the desired connections. Id., col. 2:5-7. The Gregory patents describe a method for synthesizing a complex logic circuit from a “user description specifying only signals and the circumstances under which the signals are produced, i.e., without requiring the designer to specify the hardware components or connections needed to implement them. As set forth below, the patents claim a method for taking two types of HDL statements, “flow control statements” and “directive statements,” see id., col. 62:6264, and converting them into “assignment conditions,” id. col. 68:2,4 which, in turn, are used to determine the appropriate hardware and connections.

Claim 1 of the ’841 patent, which is representative of the asserted claims, states:

1. A method for converting a hardware independent user description of a logic circuit, that includes flow control statements including an IF statement and a GOTO statement, and directive statements that define levels, of logic signals, into logic circuit hardware components comprising:
converting the flow control statements and directive statements in the user description for a logic signal Q into an assignment condition AL(Q) for an asynchronous load function AL() and an assignment condition AD(Q) for an asynchronous data function AD(); and
generating a level sensitive latch when both said assignment condition AL(Q) and said assignment condition AD(Q) are non-constant;
wherein said assignment condition AD(Q) is a signal on á data input line of said flow through latch;
said assignment condition AL(Q) is a signal on a latch gate line of said flow through latch; and
an output signal of said flow through latch is said logic signal Q.

Id., col. 62:60-col. 63:12.

Each of the steps in the claimed methods can be performed by a skilled designer either mentally or with pencil and paper, and the examples in the patents were created by the inventors without use of a computer. Although the claims themselves do not expressly call for a computer or other piece of equipment, the method is primarily intended for use with a computer, and the patents append source code for a computer program implementing the claimed inventions. (See Deck of Maria Beier, filed October 3, 2014, Ex. F (Deposition of Russ Segal) at 26:13-27 (stating “we emulated what a computer would do in order to generate these tables”); see also ’841 Patent, col. 9:42-45 (stating “[t]he system and method of this invention are operable in a computer system that includes a data input device, such as a keyboard, a processing unit, and an output display device”).

LEGAL STANDARD

Pursuant to Rule 56 of the Federal Rules of Civil Procedure, a “court shall [962]*962grant summary judgment if the movant shows that there is no genuine issue as to any material fact and that the movant is entitled to judgment as a matter of law.” See Fed.R.Civ.P. 56(a).

The Supreme Court’s 1986 “trilogy” of Celotex Corp. v. Catrett, 477 U.S. 317, 106 S.Ct. 2548, 91 L.Ed.2d 265 (1986), Anderson v. Liberty Lobby, Inc., 477 U.S. 242, 106 S.Ct. 2505, 91 L.Ed.2d 202 (1986), and Matsushita Electric Industrial Co. v. Zenith Radio Corp., 475 U.S. 574, 106 S.Ct. 1348, 89 L.Ed.2d 538 (1986), requires that a party seeking summary judgment show the absence of a genuine issue of material fact. Once the moving party has done so, the nonmoving party must “go beyond the pleadings and by [its] own affidavits, or by the depositions, answers to interrogatories, and admissions on file, designate specific facts showing that there is a genuine issue for trial.” See Celotex, 477 U.S. at 324, 106 S.Ct. 2548 (citation and quotation omitted). “When the moving party has carried its burden under Rule 56(c), its opponent must do more than simply show that there is some metaphysical doubt as to the material facts.” Matsushita, 475 U.S. at 586, 106 S.Ct. 1348. “If the [opposing party’s] evidence is merely colorable, or is not significantly probative, summary judgment may be granted.” Liberty Lobby, 477 U.S. at 249-50, 106 S.Ct. 2505 (citations omitted).

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Bluebook (online)
78 F. Supp. 3d 958, 2015 U.S. Dist. LEXIS 6333, 2015 WL 269116, Counsel Stack Legal Research, https://law.counselstack.com/opinion/synopsys-inc-v-mentor-graphics-corp-cand-2015.