Atmel Corp. v. Silicon Storage Technology, Inc.

76 F. App'x 298
CourtCourt of Appeals for the Federal Circuit
DecidedSeptember 12, 2003
DocketNos. 02-1522, 02-1523
StatusPublished
Cited by2 cases

This text of 76 F. App'x 298 (Atmel Corp. v. Silicon Storage Technology, Inc.) is published on Counsel Stack Legal Research, covering Court of Appeals for the Federal Circuit primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Atmel Corp. v. Silicon Storage Technology, Inc., 76 F. App'x 298 (Fed. Cir. 2003).

Opinion

DECISION

SCHALL, Circuit Judge.

Atmel Corporation (“Atmel”) sued Silicon Storage Technology, Inc. (“SST”) in the United States District Court for the Northern District of California for infringement of, inter alia, U.S. Patent No. 4,511,811 (“the ’811 patent”) and U.S. Patent No. 4,673,829 (“the ’829 patent”). After a jury found that SST had willfully infringed both patents and that the patents were not invalid, and after the district court denied SST’s post-verdict motion for judgment as a matter of law (“JMOL”), the district court entered final judgment in favor of Atmel against SST, awarding Atmel compensatory damages, enhanced damages, and prejudgment interest. Atmel Corp. v. Silicon Storage Tech., Inc., No. 96-00039 (N.D.Cal. June 21, 2002) (rule 54(b) judgment). The district court previously had denied Atmel’s request for attorney fees, see Atmel Corp. v. Silicon Storage Tech., Inc., 202 F.Supp.2d 1096 (N.D.Cal.2002) (order regarding pre-judgment interest, enhanced damages, and attorney fees) (“Enhanced Damages and Attorney Fees Order”), and had sanctioned Atmel under Rule 26(g) of the Federal Rules of Civil Procedure, see Atmel Corp. v. Silicon Storage Tech., Inc., No. 96-00039 (N.D.Cal. Aug.7, 2001) (order awarding sanctions) (“Sanctions Order”).

SST appeals from the district court’s judgment, raising issues relating to infiingement, validity, damages, and some of the district court’s evidentiary rulings. For its part, Atmel cross-appeals, raising issues relating to enhanced damages, its request for attorney fees, and the award of sanctions against it. We affirm the district court’s judgment in all respects.

DISCUSSION

I. Background

Atmel is the owner of the ’811 and the ’829 patents. The two patents have substantially the same specification, share the same figures, and contain only one claim each. In fact, the claim limitations of the patents that are at issue in this case are substantially identical. Consequently, unless otherwise indicated, all references in this opinion are to the specification and claim of the ’811 patent.

The patents are directed to programmable semiconductor memory chips, such as an erasable programmable read-only memory (“EPROM”) or an electrically erasable programmable read-only memory (“EEP-ROM”). ’811 patent, col. 3,11. 11-17. Such devices are composed of an array of memory cells and circuitry dedicated to writing, erasing, or reading information stored in specific memory cells. In order to program or erase designated memory cells, the circuitry must increase the voltage on a selected conductive line to a relatively high voltage, i.e., higher than 5 volts. Although there may be a power supply on the device, that power supply may not be able to generate a voltage higher than 5 volts. Accordingly, a power supply located off-chip traditionally provides the additional power needed to perform the programming and erasing operations. In order to reduce cost, size, and weight, it is preferable to generate the required high voltage on-chip from the primary low voltage power supply. The disadvantage of doing so is that on-chip devices are subject to voltage leaking from the on-chip power supply through the large number of unselected conductive lines. For example, in a 16K-bit memory chip arranged in a 128 x 128 bit array, there are 128 lines. Since only one line is selected for programming any [301]*301one byte, there are 127 unselected lines during any programming cycle through which the voltage can leak.

The ’811 and the ’829 patents recognize the foregoing problems and disclose a circuit for increasing the voltage on the selected line without the use of an external voltage supply while also preventing leakage to the unselected lines. Figure 2 of the ’811 patent, which is reproduced below, discloses such a circuit, which is sometimes referred to as a “charge pump” or a “pumping circuit”:

[[Image here]]

There are two different modes of operation of this circuit: (1) when line 8 is selected to have its voltage increased (“selected mode”); and (2) when line 8 is left unselected and not permitted to receive the transfer of charge from the high voltage generator circuit 34 (the “unselected mode”).

In the “selected mode,” the NOR predecoder 10 and post-decoder 20 identify line 8 as the addressed line and place an initial voltage on it. ’811 patent, col. 5, II. 43-53. This initial voltage causes transistor 40 to turn on, thus permitting charge to pass from the high-voltage generator circuit 34 through transistor 40 to node 42. The amount of charge passed to node 42 increases the voltage on node 42, which causes capacitor 44 to turn on. Then, when oscillator 38 cycles high, i.e., when it transitions to a high voltage (e.g., 5 volts), it raises the voltage on node 42. As a result, transistor 40 no longer conducts, but transistor 46 conducts the charge on node 42 to word line 8. This charge raises the voltage on the word line by a relatively small amount (e.g., 0.5 volts). When the oscillator 38 transitions to a low voltage, [302]*302transistor 46 turns “off’ and transistor 40 turns “on” allowing more charge to pass from the high voltage source to node 42. Subsequently, when the oscillator 38 goes high again, the process repeats, i.e., the voltage on node 42 increases, transistor 46 conducts again, and transfers the packet of charge to the selected line 8. By repeating this process many times, the voltage on the selected line 8 is incrementally raised in a stepwise fashion. In the unselected mode, line 8 is not selected and a switching device (transistor 40 or 46) blocks the leakage of voltage, by clamping the unselected line 8 to zero volts.

Claim 1 of the ’811 patent, the only claim at issue in this appeal, is as follows:

1. An apparatus for selectively increasing the voltage on one or more of a plurality of conductive lines having inherent distributed capacitance disposed in a semiconductor circuit comprising: means disposed on said semiconductor circuit for selecting one or more of said conductive lines;
high voltage generating means disposed on said semiconductor circuit for generating a high voltage from a lower voltage power supply connected to said semiconductor circuit; voltage pulse generating means disposed on said semiconductor circuit for generating voltage pulses;
means for capacitively coupling voltage pulses from said voltage pulse generating means to a voltage node in said semiconductor circuit; transfer means responsive to said selecting means and connected to said voltage node for transferring increments of charge from said high voltage generating means to the inherent distributed capacitance in selected ones of said conductive lines in response to said voltage pulses;
said transfer means including switching means cooperating with said selecting means for blocking substantially all of the flow of current through and transfer of charge from said high voltage generating means to said conductive lines which are unselected.

’811 patent, col. 8, II. 17-45.

II. Procedural History

SST manufactures EEPROM circuits that also charge a selected line while preventing leakage to unselected lines. On January 3, 1996, Atmel sued SST, alleging infringement of the ’811 patent.

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Bluebook (online)
76 F. App'x 298, Counsel Stack Legal Research, https://law.counselstack.com/opinion/atmel-corp-v-silicon-storage-technology-inc-cafc-2003.