Synopsys, Inc. v. Siemens Industry Software Inc.

CourtDistrict Court, N.D. California
DecidedNovember 12, 2020
Docket3:20-cv-04151
StatusUnknown

This text of Synopsys, Inc. v. Siemens Industry Software Inc. (Synopsys, Inc. v. Siemens Industry Software Inc.) is published on Counsel Stack Legal Research, covering District Court, N.D. California primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Synopsys, Inc. v. Siemens Industry Software Inc., (N.D. Cal. 2020).

Opinion

1 2 3 4 UNITED STATES DISTRICT COURT 5 NORTHERN DISTRICT OF CALIFORNIA 6 7 SYNOPSYS, INC., Case No. 20-cv-04151-WHO

8 Plaintiff, ORDER GRANTING DEFENDANT'S 9 v. MOTION TO DISMISS AS TO CLAIMS I AND II AND DENYING MOTION AS 10 AVATAR INTEGRATED SYSTEMS, TO CLAIM VI INC., 11 Re: Dkt. No. 26 Defendant.

13 INTRODUCTION 14 Defendant Avatar Integrated Systems, Inc., (“Avatar”) moves to dismiss three of six patent 15 infringement claims brought by plaintiff Synopsys, Inc. (“Synopsys”), arguing that three of the 16 asserted patents are directed to abstract mental processes or mathematics and therefore fail to 17 claim patent-eligible subject matter under 35 U.S.C. § 101. As discussed below, I conclude that 18 the ’863 and ’640 patents are directed to patent-ineligible abstract ideas, do not contain any 19 inventive concepts, and are therefore invalid under § 101. In contrast, construing all facts in favor 20 of Synopsys at the motion to dismiss stage, I conclude that the ’655 patent is directed to a specific 21 method for checking engineering change orders across multiple scenarios during the process of 22 fixing design requirement violations, which improves the efficient use of computers running chip 23 design software, and is therefore not invalid under § 101. In line with these conclusions, Avatar’s 24 motion to dismiss is GRANTED as to Claims I and II and DENIED as to Claim VI. 25 BACKGROUND 26 Avatar seeks to dismiss claims related to U.S. Patent Nos. 7,103,863 (“the ’863 patent”); 27 8,407,655 (“the ’655 patent”); and 8,407,640 (“the ’640 patent”), arguing that all three patents are 1 invalid under the Supreme Court’s Alice decision and its progeny. All three patents claim 2 inventions in the field of computer chip design and manufacturing. 3 I. THE ’863 PATENT 4 The ’863 patent, titled “Representing The Design of a Sub-Module in a Hierarchical 5 Integrated Circuit Design and Analysis System,” relates to “systems for designing and verifying 6 the contents and layout of an integrated circuit” in the field of electronic circuit fabrication. Dkt. 7 No. 1-1, Ex. 2 (“’863 patent”) at 1:19-22. The patent asserts that in the field of circuit design, the 8 design specification and implementation data that must be run through the relevant design 9 software is often so large that it either does not fit in the processing computer’s memory or is 10 prohibitively time-consuming to process. Id. 1:24-37. To solve this problem, it is industry 11 convention to use “hierarchical decomposition” or “partitioning” whereby the design data is split 12 into more manageable pieces called “blocks,” arranged in a hierarchy, which are then designed 13 and verified independently. Id. 1:38-45. However, because the individual blocks are part of a 14 larger circuit, and affect the behavior of the circuit as a whole, the software system must retain 15 sufficient information so that each block can be properly analyzed “in the context of its parent and 16 sibling blocks.” Id. 2:58-67. To reduce the amount of memory and execution time required for 17 this process, chip designers create a “block abstraction” that represents “the structure and behavior 18 of the block in sufficient detail that the interface with its parent block and its sibling blocks may 19 be correctly analyzed” without needing to retain all of the block data. Id. 20 The ’863 patent’s stated contribution is a new method for block abstraction. According to 21 the ’863 patent, existing methods for block abstraction used “reduced behavioral models to capture 22 approximate behavioral descriptions of the logical, physical, and electrical behavior of the block.” 23 Id. 5:5-10. In contrast, the ’863 patent’s “key idea is to represent the design, not with a simplified 24 mathematical model of reduced accuracy, but as a sub-set of the design data itself. The reduced 25 model consists of a copy of the original model, but with all non-essential information discarded.” 26 Id. 7:10-23. The patent asserts that “[b]y including the physical objects themselves instead of 27 simplified or worst-case models for them, no accuracy is lost.” Id. 7:39-41. 1 claim 35, an article of manufacture—both related to the block abstraction process described above. 2 In addition, the patent includes 65 dependent claims. Claim 1 appears representative and is the 3 focus of the parties’ briefing. It states: 4 1. A method used in producing a design of an integrated circuit said circuit design having cells and interconnects, said circuit having a representation that is hierarchically 5 decomposed into a top-level and a plurality of blocks, at least some of the plurality of said 6 blocks being capable of being further hierarchically decomposed and of having a parent block associated therewith, said method comprising: 7 processing a least one of said blocks such that an abstraction is created that 8 includes physical interconnect information relating to interconnects between components within said at least one block, said physical interconnect information 9 modeling parasitic electrical and physical effects of interconnects upon an 10 estimated behavior of said integrated circuit, wherein said processing includes: 11 retaining only a sub-set of all of said physical interconnect information which influences physical and electrical behavior of said parent block; and 12 Retaining only a sub-set of cells which influences a logical behavior of said 13 parent block; and 14 Utilizing said abstraction in another development phase performed on said parent block. 15 16 Id. 16:65 – 17:19. 17 II. THE ’640 PATENT The ’640 patent, titled “Sensitivity-Based Complex Statistical Modeling for Random On- 18 Chip Variation” relates to performing statistical static timing analysis on information describing a 19 circuit in the field of “integrated circuit timing analysis.” Dkt. No. 1-1, Ex. 1 (“’640 patent”). 20 Static timing analysis is a method by which chip designers verify the correctness of a chip design 21 without simulation. Dkt. No. 9, Corrected Complaint (“CC”) ¶ 15. In static timing analysis, 22 software calculates the expected timing of signals in a circuit to identify timing requirement 23 violations before manufacturing. Id. The ’640 patent describes various drawbacks to the existing 24 methods for performing statistical timing analysis and states that “[t]he need remains for a method 25 of on-chip variation modeling in statistical timing analysis that is sufficiently low cost so as to 26 encourage widespread and rapid adoption.” ’640 patent 1:32 – 2:5. 27 1 analysis on integrated circuits” that uses a “novel on-chip variation model.” Id. 2:8-10. The patent 2 contains one independent claim, claim 1, and seven dependent claims, all methods. Claim 1 3 states: 4 1.

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