Synopsys, Inc. v. Siemens Industry Software Inc.

District Court, N.D. California·Decided November 12, 2020·No. 3:20-cv-04151·Unknown

Opinion

SYNOPSYS, INC., Case No. 20-cv-04151-WHO

Plaintiff, ORDER GRANTING DEFENDANT'S v. MOTION TO DISMISS AS TO CLAIMS I AND II AND DENYING MOTION AS INC., Re: Dkt. No. 26 Defendant.

INTRODUCTION Defendant Avatar Integrated Systems, Inc., (“Avatar”) moves to dismiss three of six patent infringement claims brought by plaintiff Synopsys, Inc. (“Synopsys”), arguing that three of the asserted patents are directed to abstract mental processes or mathematics and therefore fail to claim patent-eligible subject matter under 35 U.S.C. § 101. As discussed below, I conclude that the ’863 and ’640 patents are directed to patent-ineligible abstract ideas, do not contain any inventive concepts, and are therefore invalid under § 101. In contrast, construing all facts in favor of Synopsys at the motion to dismiss stage, I conclude that the ’655 patent is directed to a specific method for checking engineering change orders across multiple scenarios during the process of fixing design requirement violations, which improves the efficient use of computers running chip design software, and is therefore not invalid under § 101. In line with these conclusions, Avatar’s motion to dismiss is GRANTED as to Claims I and II and DENIED as to Claim VI. BACKGROUND Avatar seeks to dismiss claims related to U.S. Patent Nos. 7,103,863 (“the ’863 patent”); 8,407,655 (“the ’655 patent”); and 8,407,640 (“the ’640 patent”), arguing that all three patents are invalid under the Supreme Court’s Alice decision and its progeny. All three patents claim inventions in the field of computer chip design and manufacturing. I. THE ’863 PATENT The ’863 patent, titled “Representing The Design of a Sub-Module in a Hierarchical Integrated Circuit Design and Analysis System,” relates to “systems for designing and verifying the contents and layout of an integrated circuit” in the field of electronic circuit fabrication. Dkt. No. 1-1, Ex. 2 (“’863 patent”) at 1:19-22. The patent asserts that in the field of circuit design, the design specification and implementation data that must be run through the relevant design software is often so large that it either does not fit in the processing computer’s memory or is prohibitively time-consuming to process. Id. 1:24-37. To solve this problem, it is industry convention to use “hierarchical decomposition” or “partitioning” whereby the design data is split into more manageable pieces called “blocks,” arranged in a hierarchy, which are then designed and verified independently. Id. 1:38-45. However, because the individual blocks are part of a larger circuit, and affect the behavior of the circuit as a whole, the software system must retain sufficient information so that each block can be properly analyzed “in the context of its parent and sibling blocks.” Id. 2:58-67. To reduce the amount of memory and execution time required for this process, chip designers create a “block abstraction” that represents “the structure and behavior of the block in sufficient detail that the interface with its parent block and its sibling blocks may be correctly analyzed” without needing to retain all of the block data. Id. The ’863 patent’s stated contribution is a new method for block abstraction. According to the ’863 patent, existing methods for block abstraction used “reduced behavioral models to capture approximate behavioral descriptions of the logical, physical, and electrical behavior of the block.” Id. 5:5-10. In contrast, the ’863 patent’s “key idea is to represent the design, not with a simplified mathematical model of reduced accuracy, but as a sub-set of the design data itself. The reduced model consists of a copy of the original model, but with all non-essential information discarded.” Id. 7:10-23. The patent asserts that “[b]y including the physical objects themselves instead of simplified or worst-case models for them, no accuracy is lost.” Id. 7:39-41. claim 35, an article of manufacture—both related to the block abstraction process described above. In addition, the patent includes 65 dependent claims. Claim 1 appears representative and is the focus of the parties’ briefing. It states: 1. A method used in producing a design of an integrated circuit said circuit design having cells and interconnects, said circuit having a representation that is hierarchically decomposed into a top-level and a plurality of blocks, at least some of the plurality of said blocks being capable of being further hierarchically decomposed and of having a parent block associated therewith, said method comprising: processing a least one of said blocks such that an abstraction is created that includes physical interconnect information relating to interconnects between components within said at least one block, said physical interconnect information modeling parasitic electrical and physical effects of interconnects upon an estimated behavior of said integrated circuit, wherein said processing includes: retaining only a sub-set of all of said physical interconnect information which influences physical and electrical behavior of said parent block; and Retaining only a sub-set of cells which influences a logical behavior of said parent block; and Utilizing said abstraction in another development phase performed on said parent block. Id. 16:65 – 17:19. II. THE ’640 PATENT The ’640 patent, titled “Sensitivity-Based Complex Statistical Modeling for Random On- Chip Variation” relates to performing statistical static timing analysis on information describing a circuit in the field of “integrated circuit timing analysis.” Dkt. No. 1-1, Ex. 1 (“’640 patent”). Static timing analysis is a method by which chip designers verify the correctness of a chip design without simulation. Dkt. No. 9, Corrected Complaint (“CC”) ¶ 15. In static timing analysis, software calculates the expected timing of signals in a circuit to identify timing requirement violations before manufacturing. Id. The ’640 patent describes various drawbacks to the existing methods for performing statistical timing analysis and states that “[t]he need remains for a method of on-chip variation modeling in statistical timing analysis that is sufficiently low cost so as to encourage widespread and rapid adoption.” ’640 patent 1:32 – 2:5. analysis on integrated circuits” that uses a “novel on-chip variation model.” Id. 2:8-10. The patent contains one independent claim, claim 1, and seven dependent claims, all methods. Claim 1 states: 1. A computer-implemented method of statistical static timing analysis (SSTA) comprising: receiving, by a computer, information describing a circuit, the information comprising: a first input node, a second input node, and an output node, such that there is a first path from the first input node to the output node, and a second path from the second input node to the output node, the first path and the second path converging at the output node, each path associated with a parametric delay represented as a nominal delay value and a standard deviation value, the standard deviation value representing a timing impact of local random variation; performing statistical static timing analysis (SSTA) based on on-chip variation (OCV) model, the SSTA comprising, determining a parametric delay at the output node based on a statistical maximum of parametric delay through the first path and parametric delay through the second path, wherein the statistical maximum preserves N sigma corner delay values, and determining the statistical maximum comprises: determining a nominal delay value of the parametric delay at the output node based on a maximum of: nominal delay value of the parametric delay through the first path, and nominal delay of the parametric delay through the second path; and determining a standard deviation value of the parametric delay at the output node, comprising: determining a first value as a maximum of: a weigh

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Synopsys, Inc. v. Siemens Industry Software Inc., (N.D. Cal. 2020).

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