Eidos Display, LLC v. Au Optronics Corporation

779 F.3d 1360, 113 U.S.P.Q. 2d (BNA) 1975, 2015 U.S. App. LEXIS 3681, 2015 WL 1035284
CourtCourt of Appeals for the Federal Circuit
DecidedMarch 10, 2015
Docket2014-1254
StatusPublished
Cited by25 cases

This text of 779 F.3d 1360 (Eidos Display, LLC v. Au Optronics Corporation) is published on Counsel Stack Legal Research, covering Court of Appeals for the Federal Circuit primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Eidos Display, LLC v. Au Optronics Corporation, 779 F.3d 1360, 113 U.S.P.Q. 2d (BNA) 1975, 2015 U.S. App. LEXIS 3681, 2015 WL 1035284 (Fed. Cir. 2015).

Opinion

CHEN, Circuit Judge.

Plaintiff-Appellants Eidos Display, LLC and Eidos III, LLC (Eidos) appeal from the district court’s grant of a motion for summary judgment, finding the asserted claim of U.S. Patent No. 5,879,958 (the '958 patent) to be invalid as indefinite. Because the claim, when read in light of the specification and prosecution history, informed with reasonable certainty those skilled in the art at the time the patent was filed about the scope of the claimed invention, we reverse the district court’s grant of summary judgment of indefiniteness, and remand to the district court for further proceedings consistent with our decision.

Background

Eidos alleges AU Optronics Corporation, AU Optronics Corporation America, Chi Mei Innolux Corporation, Chi Mei Op-toelectronics USA Inc., Chunghwa Picture Tubes, Ltd., Hannstar Display Corporation, and Hannspree North America, Inc. (collectively, “Display Manufacturers”) infringe claim 1 of the '958 patent. The '958 patent is directed toward manufacturing processes for an electro-optical device, such as a liquid crystal display (LCD).

The specification of the '958 patent contains 17 embodiments, each identified by a letter (A through H, J, and L through S). Each embodiment describes a manufacturing process that reduces the number of photolithographic steps in creating an LCD panel compared to prior art processes, lowering the production cost and improving yield and production efficiency. '958 patent, 1:19-3:37 (describing the prior art as containing seven photolithographic steps), 4:39-14:18 (describing the invention as containing four or five photolithographic steps), 14:31-37 (comparing the invention to the prior art). Each embodiment is broken down into a series of “forming” steps that deposit material, such as metal, insulator, or passivation material, on the substrate or previous layers, as well as a series of “photolithographic” steps that etch or remove portions of previously-formed material. For example, the seventh embodiment, identified by the letter “G,” contains five forming steps—Gl, G3, G5, G7, and G9—sequentially interspersed with five photolithographic steps—G2, G4, G6, G8, and G10. Id. at 8:33-67. The specification describes the manufacturing process for each disclosed embodiment with reference to the figures. For example, figures 54 through 63 depict the process steps of the G embodiment. Id. at 18:9-44, 35:31-36:65.

*1362 The circuitry in the LCD devices formed by the patented manufacturing processes is the same as circuitry formed by a prior art manufacturing process. Id. at 1:16-18. An example of such a prior art circuit is found in figure 169, reproduced below. Id. 1 Figure 169 shows a matrix with source wiring (SI, S2, S3, ... Sn) forming the vertical lines and gate wiring (Gl, G2, G3, ... Gn) forming the horizontal lines. Id. at 1:19-23. The source wiring is connected to a signal supply circuit to provide image data, and the gate wiring is connected to a scanning circuit to provide control signals. Id.; Appellants’ Br. at 6-7.

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Important to this appeal, the electrical connection between a source wire and the signal supply circuit is called a source wiring connection terminal. The electrical connection between a gate wire and the scanning circuit is called a gate wiring connection terminal. In an LCD panel, there are many individual source and gate wires, each with a connection terminal located at the end of the we. Appellants’ Br. at 7 (citing Eidos Display, LLC v. AU Optronics Corp., No. 6:11-cv-201 LED-JDL, 2013 WL 1559729, at *5 (E.D.Tex. Apr. 12, 2013)). During the relevant LCD manufacturing process, a non-conductive passivation film is formed on top of the wiring and connection terminals. See '958 patent, 58:34-36 (Step G7). The passivation film is then etched away to allow the scanning and signal supply circuits to connect to the terminals. See id. at 58:37-41 (Step G8). Experts for both parties agree that, at the time of the '958 patent, the only industry practice for this manufacturing process was to create individual holes, referred to as “contact holes,” through the passivation film to each connection terminal. While a single contact hole shared by all the connection terminals may have been technically possible, no expert was aware of any example or teaching where such a contact hole was ever created, and neither party put any such teaching into the record, if such a teaching exists.

The asserted claim 1 is the only issued claim in the '958 patent and recites:

1. A method for producing an electro-optical device in which an electro-optical material is put between a pair of substrates opposed to each other, at least a portion of opposing surfaces of the substrates is insulative, a plurality of source wirings and a plurality of gate wirings are formed crossing each other on the *1363 surface of one of said pair of substrates and a transparent pixel electrode and a thin film transistor are formed at each of the crossing points between the source wirings and the gate wirings, wherein the method comprises: a step G1 of forming a first metal film on the surface of said one substrate, a first photolithographic step G2 of patterning the first metal film to form a gate electrode and a gate wiring,
a step G3 of forming a first insulator film, a semiconductor film and an ohmic contact film on the surface of said one substrate after the first photolithographic step,
a second photolithographic step G4 of patterning the semiconductor active film and the ohmic contact film to form a semiconductor portion above the gate electrode in a state isolated from other portions,
a step G5 of forming a second metal film on the surface of said one substrate after the second photolithographic step, a third photolithographic step G6 of patterning the second metal film and the ohmic contact film to form a source electrode, a drain electrode and a channel portion,
a step G7 of forming a passivation film on the surface of said one substrate after the third photolithographic step, and
a fourth photolithographic step G8 of patterning the passivation film to form a contact hole reaching the gate wiring, a contact hole reaching the drain electrode and a contact hole for source wiring and gate wiring connection terminals, a step G9 of forming a transparent conductive film on the surface of said one substrate after the fourth photolitho-graphic step, and
a fifth photolithographic step G10 of patterning the transparent conductive film to form a transparent pixel electrode.

Id. at 58:5-47 (emphasis added to highlight the limitation at issue on appeal).

During Markman proceedings in front of the magistrate judge, the primary claim construction dispute focused on the last portion of step G8, “a contact hole for source wiring and gate wiring connection terminals.”

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779 F.3d 1360, 113 U.S.P.Q. 2d (BNA) 1975, 2015 U.S. App. LEXIS 3681, 2015 WL 1035284, Counsel Stack Legal Research, https://law.counselstack.com/opinion/eidos-display-llc-v-au-optronics-corporation-cafc-2015.