Wang Laboratories, Inc. v. Toshiba Corporation

993 F.2d 858
CourtCourt of Appeals for the Federal Circuit
DecidedJune 28, 1993
Docket92-1006
StatusPublished

This text of 993 F.2d 858 (Wang Laboratories, Inc. v. Toshiba Corporation) is published on Counsel Stack Legal Research, covering Court of Appeals for the Federal Circuit primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Wang Laboratories, Inc. v. Toshiba Corporation, 993 F.2d 858 (Fed. Cir. 1993).

Opinion

993 F.2d 858

26 U.S.P.Q.2d 1767

WANG LABORATORIES, INC., Plaintiff/Cross-Appellant,
v.
TOSHIBA CORPORATION; Toshiba America Electronic Components,
Inc.; Toshiba America Information Systems, Inc.,
Defendants-Appellants,
and
NEC Corporation; NEC Electronics Inc. and NEC Technologies,
Inc., Defendants-Appellants,
and
Molex Incorporated, Defendant.

Nos. 92-1006, 92-1008 and 92-1025.

United States Court of Appeals,
Federal Circuit.

May 10, 1993.
Rehearing Denied; Suggestion for Rehearing In Banc Declined
June 28, 1993.

Thomas J. Scott, Howrey & Simon, Washington, DC, argued, for plaintiff/cross-appellant. With him on the brief, were Robert F. Ruyak, Sheila R. Schreiber and Diane B. Heller. Also on the brief, were Edward A. Grayson, Michael H. Shanahan and Paul W. Sandman, Wang Laboratories, Inc., Lowell, MA.

Edward F. McKie, Banner, Birch, McKie & Beckett, Washington, DC, argued, for defendants-appellants, Toshiba Corp. With him on the brief, were Dale H. Hoscheit, Joseph M. Skerpon, Richard J. Moura and Pamela I. Banner. Howard L. Bernstein, Sughrue, Mion, Zinn, MacPeak & Seas, Washington, DC, argued, for defendants-appellants, NEC Corp. With him on the brief, were J. Frank Osha, L. Peter Bernstein and Brett S. Sylvester.

Before ARCHER, LOURIE, and CLEVENGER, Circuit Judges.

LOURIE, Circuit Judge.

This is a patent infringement suit involving two patents on memory modules. It comes to us as a consolidated appeal and cross-appeal from the August 23, 1991 judgment, 1991 WL 333696, and the October 23, 1991 amended judgment of the United States District Court for the Eastern District of Virginia, Civil No. 90-1477-A. On August 8, 1991, a jury returned a verdict in favor of Wang Laboratories, Inc., finding U.S. Patents 4,656,605 and 4,727,513 infringed by Toshiba Corporation, Toshiba America Electronic Components, Inc., and Toshiba America Information Systems, Inc. (collectively Toshiba) and NEC Corporation, NEC Electronics Inc., and NEC Technologies, Inc. (collectively NEC), and not invalid. The jury found that NEC had willfully infringed the patents in suit, while Toshiba's infringement was not willful. On August 14, 1991, the jury determined that Wang was entitled to a reasonable royalty as compensation for the infringement and determined alternative reasonable royalty rates. On August 23, 1991, the district court entered judgment in accordance with the jury verdicts, ruled that the patents were not invalid and were infringed, and awarded a reasonable royalty as damages.

Toshiba and NEC filed post-trial motions for judgment notwithstanding the verdict (JNOV),1 which the district court subsequently denied.2 Wang moved to amend the judgment as to damages; this motion was also denied. Toshiba and NEC now appeal from the district court's judgment denying JNOV on the issues of validity and infringement. Wang cross-appeals the district court's failure to amend the judgment as to the royalty rate. We affirm-in-part, reverse-in-part, and remand-in-part.

BACKGROUND

The '605 and '513 patents, both entitled "Single In-Line Memory Module," were issued in the name of James E. Clayton and assigned to Wang. The '605 patent issued on April 7, 1987, and the '513 patent on February 23, 1988 from a continuation of the application that led to the '605 patent.3

The patents relate to single in-line memory modules (SIMMs) having eight data memory chips capable of storing 8-bit binary words or bytes.4 Additionally, the memory modules include a ninth chip, which functions as a check or parity bit for error detection.5 The nine memory chips, which are packaged in plastic leaded chip carriers (PLCCs), are mounted on a single epoxy-glass printed circuit board substrate. Decoupling capacitors for suppressing voltage spikes are also mounted on the memory module substrate. Preferably, access terminals are arrayed across the bottom of the device for data input and output, data address and memory control, and device power. The '605 patent claims require that the ninth chip be interconnected with the other eight, while the '513 patent claims do not require this interconnection so that the parity chip can be written to or read from independently of the eight data chips.

The '605 patent contains one claim, which reads as follows:

A memory module for installation on a printed circuit motherboard comprising:

eight data memory chips for storing digital data, each having a data input and output, a control input, and an address input, and each being packaged in a plastic leaded chip carrier;

a ninth memory chip for storing error detection and correction information associated with the eight data memory chips, said ninth memory chip having a data input and output, a control input and an address input interconnected with those of the eight memory chips, and a control input to provide writing in or reading out of the ninth memory chip at times other than when said bytes of digital information are written into or read out of the eight data memory chips to thereby facilitate said error detection and correction operation;

an epoxy-glass printed circuit board substrate having a length and width adequate for mounting thereon only in a single row said nine memory chips and for interconnecting the control inputs and the address inputs of the memory chips so that bytes of digital information may be input to or output from the memory chips one at a time;

the substrate including thirty terminals for providing access to the data inputs and outputs, control inputs, and address inputs of the nine memory chips to enable reading and writing of bytes of digital information into and out of the eight memory chips and to enable reading and writing of error detection and correction information into and out of the eight memory chips;

support means for supporting the memory module at an angle with respect to the printed circuit motherboard when the memory module is installed thereon; and

eight decoupling capacitors, mounted on said substrate and connected between the nine memory chips, for suppressing transient voltage spikes between said memory chips.

(Emphasis added).

The '513 patent contains Claims 1 and 2, which read as follows:1. A memory module for installation on a printed circuit motherboard comprising

nine data memory chips for storing digital data, each having a data input and output, control input, and an address input, and each being packaged in a plastic leaded chip carrier, wherein said ninth memory chip is for storing detection and correction information associated with the eight data memory chips,

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993 F.2d 858, Counsel Stack Legal Research, https://law.counselstack.com/opinion/wang-laboratories-inc-v-toshiba-corporation-cafc-1993.