Tessera, Inc. v. International Trade Commission

646 F.3d 1357, 98 U.S.P.Q. 2d (BNA) 1868, 2011 U.S. App. LEXIS 10363, 2011 WL 1944067
CourtCourt of Appeals for the Federal Circuit
DecidedMay 23, 2011
Docket2010-1176
StatusPublished
Cited by36 cases

This text of 646 F.3d 1357 (Tessera, Inc. v. International Trade Commission) is published on Counsel Stack Legal Research, covering Court of Appeals for the Federal Circuit primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Tessera, Inc. v. International Trade Commission, 646 F.3d 1357, 98 U.S.P.Q. 2d (BNA) 1868, 2011 U.S. App. LEXIS 10363, 2011 WL 1944067 (Fed. Cir. 2011).

Opinion

LINN, Circuit Judge.

Tessera, Inc. (“Tessera”) filed a complaint with the United States International Trade Commission (the “Commission” or “ITC”) on December 21, 2007, under section 337 of the Tariff Act of 1980, 19 U.S.C. § 1337, alleging that eighteen respondents infringed U.S. Patent Nos. 5,663,106 (the “'106 patent”); 5,679,977 (the “'977 patent”); 6,133,627 (the “'627 patent”); and 6,458,681 (the “'681 patent”) through the importation of certain semiconductor chips. See Certain Semiconductor Chips With Minimized Chip Package Size and Products Containing Same, No. 337-TA-630, 2009 WL 3092628 (Int’l Trade Comm’n Aug. 28, 2009) (“Initial Determination”). The '681 patent was terminated from the investigation prior to hearing. Tessera appeals from the Commission’s final determination finding no section 337 violation. Certain Semiconductor Chips With Minimized Chip Package Size and Products Containing Same, No. 337-TA-630, 2010 WL 686377 (Int’l Trade Comm’n Feb. 24, 2010) (“Final Determination ”).

Of the eighteen respondents, ten remain in the case and have intervened in this *1361 appeal. The intervenors include Elpida Memory, Inc. and Elpida Memory (USA) Inc. (collectively, “Elpida”); Smart Modular Technologies, Inc.; Acer, Inc., Acer America Corporation, Nanya Technology Corporation, Nanya Technology Corporation USA, and PowerChip Semiconductor Corporation; Ramaxel Technology Ltd.; and Kingston Technology Company, Inc. (collectively, “Intervenors”). Because the Commission’s decision is supported by substantial evidence and is not contrary to law, this court affirms the determination of no violation with respect to the '106 patent, and vacates as moot the Commission’s decision regarding the '977 and '627 patents, which have now expired.

I. Background

The patents-in-suit relate to innovations in semiconductor chip packaging.

A. Technology

A semiconductor chip (“chip”) is a widely used miniaturized electronic circuit. A semiconductor package (“package”) protects these delicate chips from mechanical and thermal damage. Most modern packages protect the chip by encapsulating it with a molded plastic, generally referred to as “encapsulant.” One problem with using encapsulant, however, is that it tends to contaminate the delicate, miniature electrical terminals on the exterior of those packages. These terminals serve as an endpoint for electrically connecting the package to another device, such as a printed circuit board. These terminals become contaminated when encapsulant obstructs the terminals, preventing an effective and reliable electrical connection. The '106 patent is directed toward innovations preventing the contamination of exposed terminals on packages during encapsulation.

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Figure 1 provides an illustration of the invention described and claimed in the '106 patent. The claimed invention is directed to protecting the terminals (26) of the chip (12) from encapsulant (40). During encapsulation, the patent describes using an encapsulant barrier (28) and a protective barrier (30) to define an encapsulation area. The preferred embodiment uses a material known as “solder mask” for the protective barrier, but also permits the use of “any other means which protects the exposed terminals on the top layer.” Id. col.211.25-26, 59-61. The protective barrier protects the terminals from coming in contact with encapsulant (40) when it is injected into the encapsulation area through a fill hole (36).

Tessera asserted claims 1-4, 9-10, and 33-35 of the '106 patent. Claim 1, from which the other asserted claims depend, is set forth below with emphasis added to show the key limitation on appeal:

*1362 1. A method of encapsulating a semiconductor chip assembly having a top layer with an array of exposed terminals thereon, the terminals being electrically connected to the chip, said method comprising the steps of:
placing an encapsulant barrier adjacent the semiconductor chip assembly, said encapsulant barrier at least partially defining an encapsulation area;
providing a protective barrier in contact with said top layer for protecting the terminals on the top layer from an encapsulation material; and
introducing an encapsulation material into at least a portion of the encapsulation area so that the encapsulation material flows to fill the encapsulation area and then cures to a substantially solid condition, the protective barrier preventing the encapsulation material from contacting the terminals on the top layer. Id. col.9 11.32 — 48 (emphases added).

B. Accused Products

Each package accused of infringing the '106 patent includes a chip and a package substrate layer. The accused products fall into two categories: a first group with a polyimide-based package substrate (“|LBGA”) and a second group with a laminate-based package substrate (“wBGA”). Despite using different materials for the package substrate layer, the accused products are similar in most respects. Only Elpida imports the accused p,BGA products, whereas all intervenors import the accused wBGA products. Because the infringement determination as to the pJBGA is not challenged on appeal, this discussion will focus on the accused wBGA products.

The accused wBGA products consist of a stack of layers. The bottom-most relevant layer is the laminate substrate layer. This layer can be thought of as a solid foundational layer. A copper wiring layer is applied on top of this laminate substrate layer. This conductive copper wiring layer provides for the controlled flow of electrical signals. To prevent corrosion of the copper and the inadvertent shorting of the electrical paths, a solder mask layer is applied on top of the copper wiring layer. The solder mask layer covers both the copper wiring layer and the underlying laminate substrate layer, leaving exposed only the endpoints of each copper conductive path. These exposed copper endpoints — holes in the solder mask layer where the underlying copper wiring layer is exposed — are the terminals of the accused wBGA products. During encapsulation, a “protective barrier” comes in contact with the solder mask layer and prevents encapsulant from flowing into the holes on the solder mask layer and contaminating those terminals — the exposed areas of the underlying copper wiring layer.

C. Tessera’s Licensees

Tessera’s primary business is licensing its technology. Since the late 1990s, Tess-era has licensed the patents-in-suit to more than sixty semiconductor technology companies, including nine of the ten largest. Tessera often licenses its patents to suppliers through agreements called “TCC Licenses.”

While the terms of each TCC License vary from licensee to licensee, these TCC Licenses share several characteristics. Each TCC License calls for an upfront license fee along with running royalties to be paid at the end of a reporting period for products sold.

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646 F.3d 1357, 98 U.S.P.Q. 2d (BNA) 1868, 2011 U.S. App. LEXIS 10363, 2011 WL 1944067, Counsel Stack Legal Research, https://law.counselstack.com/opinion/tessera-inc-v-international-trade-commission-cafc-2011.