Sandisk Corporation v. Memorex Products, Inc.

415 F.3d 1278, 75 U.S.P.Q. 2d (BNA) 1475, 2005 U.S. App. LEXIS 13518
CourtCourt of Appeals for the Federal Circuit
DecidedJuly 8, 2005
Docket04-1422
StatusPublished

This text of 415 F.3d 1278 (Sandisk Corporation v. Memorex Products, Inc.) is published on Counsel Stack Legal Research, covering Court of Appeals for the Federal Circuit primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Sandisk Corporation v. Memorex Products, Inc., 415 F.3d 1278, 75 U.S.P.Q. 2d (BNA) 1475, 2005 U.S. App. LEXIS 13518 (Fed. Cir. 2005).

Opinion

415 F.3d 1278

SANDISK CORPORATION, Plaintiff-Appellant,
v.
MEMOREX PRODUCTS, INC. (formerly doing business as Memtec Products, Inc.), Defendant-Appellee, and
Pretec Electronics Corporation, Defendant-Appellee, and
Power Quotient International Co., Ltd., Defendant, and
Ritek Corporation, Defendant-Appellee.

No. 04-1422.

No. 04-1610.

United States Court of Appeals, Federal Circuit.

July 8, 2005.

Donald R. Dunner, Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P., of Washington, DC, argued for plaintiff-appellant. With him on the brief were Thomas H. Jenkins, of Washington, DC, and Erik R. Puknys, of Palo Alto, California. Of counsel on the brief were Michael A. Ladra and James C. Yoon, Wilson Sonsini Goodrich & Rosati P.C., of Palo Alto, California; and Michael A. Berta and Ariana M. Chung-Han, of San Francisco, California.

Jon B. Streeter, Keker & Van Nest, LLP, of San Francisco, California, for defendant-appellee Memorex Products, Inc. (formerly doing business as Memtec Products, Inc.). Of counsel was G. Whitney Leigh.

Ronald C. Finley, Mount & Stoelker, P.C., of San Jose, California, argued for defendant-appellee Pretec Electronics Corporation. With him on the brief were Daniel S. Mount, Alfredo A. Bismonte, and Justin T. Beck.

Alan D. Smith, Fish & Richardson P.C., of Boston, Massachusetts, argued for defendant-appellee Ritek Corporation. With him on the brief was Charles H. Sanders.

Before RADER, GAJARSA, and DYK, Circuit Judges.

GAJARSA, Circuit Judge.

SanDisk appeals the district court's judgment of no infringement in favor of Memorex, Pretec, and Ritek. The district court granted summary judgment that various Flash memory devices made by these defendants did not infringe independent claims 1 or 10—or various claims depending therefrom—in SanDisk's U.S. Patent No. 5,602,987 to Flash EEprom systems. The trial court ruled that the claims at bar did not contemplate or allow for a Flash memory system in which some EEprom memory cells are grouped into sectors that are not partitioned into user and overhead data portions. As the record showed that the defendants' products contained sectors of memory cells lacking such partitions, the trial court determined that these defendants could not infringe. We conclude that the trial court misread the claims at issue, and erred in finding a prosecution disclaimer in support of its reading. We further reject the contention that judicial estoppel forecloses SanDisk's claim construction arguments on appeal. Thus, we vacate the judgment and remand for further proceedings.

I.

A.

SanDisk Corp. ("SanDisk") owns U.S. Patent No. 5,602,987 to Flash EEprom systems ("the '987 patent").1 The '987 patent issued on February 11, 1997, and describes methods for using EEproms as non-volatile solid state computer memory. A non-volatile memory retains its contents even after power is shut off. This "flash memory" has many applications, including the memory used in digital cameras, PDAs, memory sticks or MP3 players.

Flash EEproms can sustain only a limited number of writes and erases before they fail. The '987 system and methods include innovations directed at improving flash memory performance and extending EEprom life. The patent focuses, in particular, on improving the memory system architecture over the prior art. The memory architecture generally concerns how the memory system solves the problem of storing or retrieving specific information from the memory cells. See '987 patent, col. 5, II. 4-21. If the architecture can be designed to minimize the number of times each EEprom memory cell is erased and rewritten, then that solution can extend the useful life of the integrated circuit. If the architecture allows for faster operations, then the EEprom performance will improve.

The '987 patent addresses these issues in at least two ways relevant to this appeal. First, it introduces a multi-sector erase function. In earlier systems either every memory cell in an EEprom would be written or erased in one operation, or only a single "sector" could be erased in one operation. See '987 patent, col. 4, II. 46-63. Where not all the information was to be erased, systems that operated only on the entire chip had to read that information out, store it in a temporary location (typically a different, volatile memory or RAM), erase the entire chip, and then write the information back into the EEprom memory. Id. The other approach, operating sequentially on individual sectors, proved time-consuming.

The '987 patent describes a different way of organizing the memory storage, and in particular arranges memory cells into "sectors" akin to the physical "sectors" used for storage on magnetic disk drives. The '987 patent allows the operator to select multiple sectors for simultaneous erase. The defining feature of the "sector" of memory cells is that all cells within the sector are erased together. See '987 patent, col. 1, II. 65-66 ("[A]n array of Flash EEprom cells on a chip is organized into sectors such that all cells within each sector are erasable at once."); id. at col. 5, II. 9-11 ("The memory in each Flash EEprom chip is partitioned into sectors where all memory cells within a sector are erasable together."). Put differently, the "sector" is the "basic unit of erase." The '987 patent illustrates this architecture, as implemented on a single EEprom or integrated circuit (chip), in Fig. 3A:

NOTE: OPINION CONTAINING TABLE OR OTHER DATA THAT IS NOT VIEWABLE

Although the block diagram in Fig. 3A illustrates the description of multiple sectors on a single chip, the multi-sector erase feature is not limited to individual EEproms. As the '987 patent notes, "the selected sectors [for erase] may be confined to one EEprom chip or be distributed among several chips in a system. The sectors that were selected will all be erased together." '987 patent, col. 5, II. 16-19. Because this allows more intelligent use of the memory, avoiding needless erases, it improves performance and extends the operational life of the EEproms. As the patent explains, "[t]his is faster and more efficient than prior art schemes where all the sectors must be erased every time or only one sector at a time can be erased. The invention further allows any combination of sectors selected for erase to be deselected and prevented from further erasing during the erase operation." '987 patent, col. 2, II. 4-7.

Second, the architecture described in the '987 patent further requires "partitioning" the "sectors" into at least two components — one for "user data," and a second for "overhead." "User data" means the information that the processor stores or on which it operates. "Overhead data" refers to administrative information used by the memory controller, such as data address information (typically the information included in a header), memory cell defect maps, error correction code, and so on. The memory allocation in a "typical" sector is illustrated in Fig. 5:

NOTE: OPINION CONTAINING TABLE OR OTHER DATA THAT IS NOT VIEWABLE

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415 F.3d 1278, 75 U.S.P.Q. 2d (BNA) 1475, 2005 U.S. App. LEXIS 13518, Counsel Stack Legal Research, https://law.counselstack.com/opinion/sandisk-corporation-v-memorex-products-inc-cafc-2005.