Promos Technologies, Inc. v. Samsung Electronics Co., Ltd.

Court of Appeals for the Federal Circuit·Decided April 6, 2020·No. 19-1343·Unpublished

Opinion

Case: 19-1343 Document: 43 Page: 1 Filed: 04/06/2020

NOTE: This disposition is nonprecedential.

United States Court of Appeals for the Federal Circuit ______________________

PROMOS TECHNOLOGIES, INC., Appellant

v.

SAMSUNG ELECTRONICS CO., LTD., Appellee ______________________

2019-1343 ______________________

Appeal from the United States Patent and Trademark Office, Patent Trial and Appeal Board in No. IPR2017- 01412.

-----------------------------------------------------------------

SAMSUNG ELECTRONICS CO., LTD., Appellee ______________________

2019-1344 ______________________ Case: 19-1343 Document: 43 Page: 2 Filed: 04/06/2020

Appeal from the United States Patent and Trademark Office, Patent Trial and Appeal Board in No. IPR2017- 01413. ______________________

Decided: April 6, 2020 ______________________

KEVIN CHRISTOPHER JONES, TechKnowledge Law Group LLP, Redwood City, CA, argued for appellant. Also represented by CRAIG R. KAUFMAN.

NAVEEN MODI, Paul Hastings LLP, Washington, DC, argued for appellee. Also represented by CHETAN BANSAL, STEPHEN BLAKE KINNAIRD, JOSEPH PALYS. ______________________

Before O’MALLEY, REYNA, and WALLACH, Circuit Judges. Opinion for the court filed by Circuit Judge O’MALLEY. Dissenting opinion filed by Circuit Judge REYNA. O’MALLEY, Circuit Judge. In two inter partes review proceedings requested by Samsung Electronics Co. (“Samsung”), the U.S. Patent Trial and Appeal Board (“the Board”) invalidated all chal- lenged claims of U.S. Patent No. 6,069,507 (the “’507 pa- tent”), which is assigned to ProMOS Technologies, Inc. (“ProMOS”). J.A. 3; J.A.II. 3. 1 The Board found the chal- lenged claims unpatentable as anticipated and obvious.

1 This opinion primarily cites to the briefing and ap- pendix from the -1343 appeal because the briefing and ap- pendices for the two appeals are substantially identical on the claim construction issue. Any citations to the -1344 briefing and appendices will use the modifier “II,” e.g., “J.A.II.,” “Appellant Br. II,” “Appellee Br. II” Case: 19-1343 Document: 43 Page: 3 Filed: 04/06/2020

PROMOS TECHS., INC. v. SAMSUNG ELECS. CO., LTD. 3

ProMOS appeals the Board’s final written decisions, argu- ing that the Board’s invalidity findings are erroneous be- cause its construction of the “maintaining” limitation is erroneous. Because we agree with the Board’s construc- tion, we affirm the Board’s decisions. I. BACKGROUND A. The Technology A clock signal is a type of periodic signal that oscillates between low and high voltages, and is often used to coordi- nate or synchronize different parts of a circuit. J.A. 227. The most common type of clock signal is in the form of a square wave, usually with a fixed, constant frequency:

J.A. 227. The period (or cycle) of a clock signal is the dura- tion between one LOW-to-HIGH transition, also called a “rising edge,” and the next LOW-to-HIGH transition. J.A. 227. The HIGH-to-LOW transition is similarly called a “falling edge.” One period of a clock signal spans a 360˚ phase. J.A. 228. When the rising and falling edges of two clock signals do not occur at the same time, the two signals are not “phase-aligned.” J.A. 228. This difference is known as a “phase difference.” One challenge associated with digital circuits is “clock skew”—that is, when a clock signal originating from a given source arrives at different components in a circuit at different times. J.A. 229–30. Clock skew may be caused by a variety of spatial or physical conditions, e.g., differing lengths of wire for conducting clock signals to respective components. J.A. 230. When circuit components have dif- ferent perceptions of timing due to clock skew, this may lead to undesirable circuit behavior. J.A. 230. For exam- ple, if two circuit components—which are designed to Case: 19-1343 Document: 43 Page: 4 Filed: 04/06/2020

execute actions simultaneously—receive copies of a clock signal that are not phase-aligned due to clock skew, the ac- tions will occur sequentially. One way to address this issue is through a system known as a “delay locked loop” (“DLL”). A DLL, via a “phase detector,” determines how much of a phase differ- ence there is between two clock signals: a reference (or in- put) clock and an output (or feedback) clock. The DLL then employs a “voltage variable delay line” to delay the input data until it is synchronized with the reference clock. B. The ’507 Patent The ’507 patent, entitled “Circuit and Method for Re- ducing Delay Line Length in Delay-Locked Loops,” relates to DLLs and “more particularly to reducing delay line length in DLLs.” ’507 patent, col. 1 ll. 12–13. Figure 1 of the patent provides an example of a “typical digital DLL” at the time of the invention.

In this “typical digital DLL,” a phase detector 12 deter- mines if a phase difference exists between the buffered in- put and feedback clock signals, “CKI” and “CKF.” ’507 patent, col. 1 ll. 19–33. If there is a nonzero phase differ- ence between the two signals, the system shifts the Case: 19-1343 Document: 43 Page: 5 Filed: 04/06/2020

PROMOS TECHS., INC. v. SAMSUNG ELECS. CO., LTD. 5

buffered input clock signal by adjusting the shift register 14 to select sufficient delay through delay line 16. ’507 pa- tent, col. 1 ll. 29–33. This added delay synchronizes the input and feedback clock signals. Id. Although DLLs can resolve the problems associated with clock skew, they generally require long delay lines to achieve sufficient coverage of frequency ranges and guar- antee desired resolution. ’507 patent, col. 1 ll. 16–18. This increased delay line length may demand larger silicon area requirements and higher power consumption. ’507 patent, col. 1 ll. 42–44. Increased delay line length may also cause other problems, such as a longer lock-in time and greater high frequency signal distortion. ’507 patent, col. 1 ll. 44– 46. The ’507 patent proposes a “more elegant and cost ef- fective” solution for reducing delay line length in a DLL. Figure 2, the only embodiment described in the written de- scription, illustrates a “digital DLL 24 in accordance with the present invention.” ’507 patent, col. 2 ll. 49–50.

The DLL 24 has an additional phase detector 30, which determines a phase difference between the buffered input clock signal CKI and a feedback clock signal CKF. ’507 pa- tent, col. 2 ll. 61–67. If the second phase detector 30 Case: 19-1343 Document: 43 Page: 6 Filed: 04/06/2020

determines that the difference between the feedback clock signal CKF and the buffered input clock signal CKI is within a 180˚ phase difference, the second phase detector controls the switch 28 to be at position (1), as seen above. Under this configuration, clock signal CKI is provided as an input to the delay line 16. ’507 patent, col. 2 l. 61–col. 3, l. 6. But if the phase difference between the two clock signals is greater than 180˚, the second phase detector con- trols switch 28 to be at position (2). Under this new config- uration, the clock signal CKI is inverted by inverter 26 and then provided as an input to the delay line. ’507 patent, col. 3 ll. 8–15. “Through the inversion, the phase difference needing to be compensated by the delay line 16’ is made less than 180˚” which decreases the length of the delay line by “approximately one-half the length that a typical DLL would require for comparable clock deskewing needs.” ’507 patent, col. 3 ll. 11–18. Independent claim 10 recites: A method for reducing delay line length in a digital delay locked loop (DLL), the method comprising: determining a phase difference between an input clock signal and a feedback clock sig- nal; maintaining the phase difference between the input clock signal and the feedback clock signal [within2] approximately 180˚,

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