Neomagic Corporation v. Trident Microsystems, Inc.

287 F.3d 1062, 62 U.S.P.Q. 2d (BNA) 1482, 2002 U.S. App. LEXIS 7005, 2002 WL 563368
CourtCourt of Appeals for the Federal Circuit
DecidedApril 17, 2002
Docket01-1631
StatusPublished
Cited by43 cases

This text of 287 F.3d 1062 (Neomagic Corporation v. Trident Microsystems, Inc.) is published on Counsel Stack Legal Research, covering Court of Appeals for the Federal Circuit primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Neomagic Corporation v. Trident Microsystems, Inc., 287 F.3d 1062, 62 U.S.P.Q. 2d (BNA) 1482, 2002 U.S. App. LEXIS 7005, 2002 WL 563368 (Fed. Cir. 2002).

Opinion

CLEVENGER, Circuit Judge.

In this patent infringement suit, Neo-Magic Corp. appeals from a decision of the District Court for the District of Delaware granting summary judgment of nonin-fringement to Trident Microsystems, Inc. (“Trident”). NeoMagic Corp. v. Trident Microsystems, Inc., 129 F.Supp.2d 689, 698 (D.Del.2001). We affirm-in part, vacate-in-part, and remand.

I

The integrated circuit technology in this case involves a graphics controller, also called a graphics engine, which controls the display of graphics on computer monitors. The graphics controller takes data from the computer’s central processing *1064 unit (“CPU”) and transforms it into information to be displayed on the monitor. The controller functions together with the dynamic random access memory (“DRAM”). The graphics controller shunts data to the DRAM, which stores it until it is needed for display purposes, and the controller then retrieves the data as needed and displays it on the monitor.

Prior art devices placed the graphics controller and the DRAM on separate chips that were joined together through conductive signal lines that formed data paths between the chips. A block diagram of the dual-chip prior art graphics controller is shown below.

[[Image here]]

The greater the number of data paths, the higher the speed of the transfer between the chips — one data path allows one bit of information to travel at a time. Though acceptable for desktop computers, where size is unimportant (relative to notebook computers) and power is unproblematic (because desktop computers plug into a wall outlet), the dual-chip design proved troublesome for notebook computers. Notebook computers must be light in weight and small in size to allow portability, and lean in power draw to increase battery life. The greater the number of chips and data paths, the greater the power draw of the overall system. And a dual-chip design takes up more space on the motherboard than would a single chip. Thus, because of power and size constraints, a dual-chip graphics controller in notebook computers could not achieve a level of performance that rivaled desktop computers.

*1065 In 1993, Deepraj Puar and Ravi Ranga-nathan, the inventors in this case, set about creating a graphics controller for notebook computers that would perform on a par with or better than desktop computers. Their goal was to turn a two-chip system into a one-chip system by putting the graphics engine and the DRAM on the same chip. A block diagram of their one-chip system is shown below.

The one-chip goal was not new, but until Puar and Ranganathan’s contributions, no one had succeeded in achieving it. The problem is that the DRAM and the graphics engine are electrically incompatible in that, according to the conventional wisdom of the time, the DRAM creates unacceptable interference (noise) with the logic portions of the graphics controller if the two are on the same chip. Puar and Rangana-than developed a way to put the two components on the same chip while isolating the graphics controller components from the noise created by the DRAM. The result was a graphics controller with high speed — a 128 bit interface — and 7.3 megabits of DRAM that was lighter and faster than the prior art versions.

The inventors decided to build their one-chip system by using a conventional DRAM process, a process that utilizes a so-called on-chip generator to bias the substrate — in this case a p-type semiconductor 1 — at a voltage VBB. The on-chip *1066 generator creates electrical noise in the substrate that interferes with the logic circuits in the graphics controller. Noise from the DRAM can cause a phenomenon known as latchup, which disables the transistors in the graphics controller’s logic gates and keeps these gates from performing their respective functions. The noise also interferes with the analog circuits in the graphics controllers.

The inventors’ solution to the noise problem was twofold. First, they designed a new circuit for the logic gates. The new circuit decouples the voltage source for the logic gates from the voltage source for the substrate, thereby preventing latchup from disabling the transistors. In essence, because the voltage source for the logic gate transistors is separate from that for the substrate, the noise no longer affects the logic gates.

As for the analog circuits, the inventors’ solution to the noise problem was to place them in an n-well, an n-type region created on a p-type semiconductor. The interface between the p-type semiconductor substrate and the n-type semiconductor in the n-well, called a p-n junction, can be reverse-biased so that components in the n-well are electrically isolated from the p-type substrate, and vice-versa. Because an understanding of reverse-biasing is crucial to our analysis of the district court’s claim construction, we briefly explain the way in which this process results in isolation of the components in the p-region from those in the n-region.

At a p-n junction, the negative and positive charge carriers flow towards the interface between the p- and n-regions.' Some negative charge carriers (free electrons) will then combine with positive charge carriers (holes) at the edge of the p-type region. As illustrated in the figure below, the combination of free electrons with holes at the interface creates a space-charge region, which is called a “depletion-region” due to the relative scarcity of free charge carriers.

Schematic diagram of a p-n junction under thermal equilibrium.

The depletion region consists of a negatively-charged section at the edge of the p-region where the free electrons have congregated and combined with holes, and a positively-charged section at the edge of the n-region, which has been depleted of free electrons. Though there is no net charge on the substrate, the charge separation across the depletion region creates an electric field across the junction run-

*1067 ning from positive to negative, and gives rise to a potential barrier between the p-side and the n-side of the p-n junction.

A p-n junction will pass an electric current in only one direction. Current will flow if the voltage applied to the p-region is more positive than that applied to the n-region; applying current in this way is called forward-biasing. Conversely, reverse-biasing occurs when the voltage in the p-region is negative with respect to that in the n-region, ie., the exact opposite of the conditions required for forward-biasing. Reverse-biasing does not require the application of an absolute negative voltage to the p-region. 2 All that is necessary is that the voltage applied to the p-region be less positive than that applied to the n-region. Reverse-biasing expands the depletion region, which raises the potential barrier between the p- and n-regions and blocks the flow of current across the junction.

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287 F.3d 1062, 62 U.S.P.Q. 2d (BNA) 1482, 2002 U.S. App. LEXIS 7005, 2002 WL 563368, Counsel Stack Legal Research, https://law.counselstack.com/opinion/neomagic-corporation-v-trident-microsystems-inc-cafc-2002.