In re Waldbaum

457 F.2d 997, 59 C.C.P.A. 940, 173 U.S.P.Q. (BNA) 430, 1972 CCPA LEXIS 345
CourtCourt of Customs and Patent Appeals
DecidedApril 20, 1972
DocketNo. 8619
StatusPublished
Cited by16 cases

This text of 457 F.2d 997 (In re Waldbaum) is published on Counsel Stack Legal Research, covering Court of Customs and Patent Appeals primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
In re Waldbaum, 457 F.2d 997, 59 C.C.P.A. 940, 173 U.S.P.Q. (BNA) 430, 1972 CCPA LEXIS 345 (ccpa 1972).

Opinions

BaldwiN, Judge.

This appeal is from the decision of the Patent Office Board of Appeals, affirming a rejection of claims 1-15 in appellant’s application.1 No claims have been allowed.

The Invention

The invention relates to a method of analyzing data words to determine the number of l’s they contain.2 The specification states that there are numerous needs for such analyses in computer-controlled systems, a traffic study on telephone lines being given as exemplary. Apparently methods of analyzing data words have been known, but appellant asserts that his method requires fewer operations and therefore takes less time.

The process is carried out by taking particular advantage of two features allegedly available in at least certain prior art computers: a capability of handling what we shall call an EXAMINE instruction, and an address memory device referred to by appellant as a J-register.

A computer program is in essence a series of instructions for the computer to follow. Typical instructions might be to add a certain number to the data being worked on, or multiply the data by a number, or compare the data to another number to see which is larger, etc. [942]*942When a program is fed into a computer, each instruction is stored in an addressed part of its memory circuitry. "When the data to be worked on is fed into the computer, it is treated in accordance with those stored instructions. Normally, the instructions are performed in the sequence of their addresses in the computer’s memory. However, some instructions may require that the sequence not be adhered to and that the data should be treated in accordance with an instruction other than the nest one in line.

The EXAMINE instruction causes the computer to perform several operations. First it examines the data word being analyzed and determines whether all the bits are O’s. If the bits are all O’s, the computer is instructed to jump to the address of that set of instructions which governs certain final calculation steps in appellant’s process. If the word contains one or more l’s, the EXAMINE instruction requires the computer to change the least significant 1 (the 1 appearing farthest to the right in the data word) to an O. The computer then goes on to the instruction at the next consecutive address.

The J-register is a device which is used when there is a jump out of the regular order of instructions. Whenever an instruction requires the computer to go to an instruction address other than that of the next consecutive instruction, the address of the next consecutive instruction is recorded in the J-register. For example, assume that there is an EXAMINE instruction located at address number 100 in a computer, and that the address of the instruction governing the final calculations is address number 500. If the data word being analyzed is “0000” when the computer arrives at the EXAMINE instruction, the word will be analyzed, it will be determined that the word contains no l’s, and the computer will therefore be required to jump to the instruction at address number 500. Normally the computer would have followed the instructions in sequential order, i.e., it would have followed the instruction at address number 100, then followed the instruction at address number 101, etc. Since there has been a jump out of the sequential order, the address of the next consecutive instruction, address number 101, is stored in the J-register.- In other words, whenever there is a jump, the J-register records the address the machine would have gone to next if there hadn’t been a jump.

These then are the special tools appellant uses to simplify the determination of the number of l’s in a data word. Both the EXAMINE instruction and the J-register are alleged by applicant to have been previously known for other uses, the specification specifically referring to a copending application which discloses a computer purportedly containing these options.

[943]*943The way appellant analyzes data words is by placing a number of EXAMINE instructions in consecutive addresses in a computer which has the J-register. As a data word goes through the sequence of EXAMINE instructions, it loses its rightmost 1 as each instruction is carried out. Eventually the last 1 in the data word will be cancelled out. The next EXAMINE instruction will detect all 0’s in the word and will therefore cause the computer to jump to the instructions governing the final calculations. Since a jump is made, the address of the next consecutive instruction is placed in the J-register. The address of the last EXAMINE instruction used, minus the address of the first EXAMINE instruction in the sequence, gives the number of l’s which were contained in the data word.

As an example, the analysis of the data word “1010” could go as follows: Since the data word has only four digits, only four EXAMINE instructions will be necessary. These instructions must be placed in consecutive addresses in the computer’s memory, for example, at address numbers 100,101,102 and 103. When our data word is analyzed by the EXAMINE instruction at address number 100, it will be determined that not all of the bits are 0’s. The rightmost 1 will be changed to an 0, changing our word to “1000,” and the computer will go on to the instruction at address number 101. In following the EXAMINE instruction at address number 101, the computer will again find that not all of the bits in the word are 0’s, so the computer will change the rightmost 1 to an 0, making our word now “0000,” and go on to the instruction at address number 102. In following the EXAMINE instruction at address number 102, the computer will find that all of the bits in our word are now 0’s. The address of the next consecutive instruction, 103, will therefore be placed in the J-register and the computer will jump to the instruction governing the final calculating steps. These final calculating steps constitute merely the manipulation of the number stored in the J-register and the address of the first EXAMINE instruction in the sequence. Since the address stored in the J-register (here 103) minus 1 always gives the point in the sequence where it was determined that all of the l’s had been changed to 0’s (here 102), that number minus the address of the first EXAMINE instruction in the sequence (100) will always give the number of.l’s originally contained in the data word (2).

The above explanation of appellant’s process is at best vastly oversimplified, but it is enough to show the type of process we are dealing with, and that is all the background necessary here.

Claim 1 is sufficiently representative:

1. A method for controlling the operation of a data processor to determine the number of l’s in a data word; said data processor including a memory [944]

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457 F.2d 997, 59 C.C.P.A. 940, 173 U.S.P.Q. (BNA) 430, 1972 CCPA LEXIS 345, Counsel Stack Legal Research, https://law.counselstack.com/opinion/in-re-waldbaum-ccpa-1972.