Harris Corp. v. Atmel Corp.

14 F. Supp. 2d 821, 1998 U.S. Dist. LEXIS 12082, 1998 WL 458236
CourtDistrict Court, E.D. Virginia
DecidedAugust 3, 1998
DocketC.A. 98-98-A
StatusPublished

This text of 14 F. Supp. 2d 821 (Harris Corp. v. Atmel Corp.) is published on Counsel Stack Legal Research, covering District Court, E.D. Virginia primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Harris Corp. v. Atmel Corp., 14 F. Supp. 2d 821, 1998 U.S. Dist. LEXIS 12082, 1998 WL 458236 (E.D. Va. 1998).

Opinion

MEMORANDUM OPINION

ELLIS, District Judge.

Harris’ 1 United States Patent No. 4,349,-584 (“the ’584 patent”) is one of eight semiconductor patents at issue in this litigation. Now before the Court are the parties’ cross *823 motions for summary judgment on the subject of infringement of the ’584 patent. At issue, essentially, is the proper construction of two disputed terms within claim 1 of the patent, and, of course, a determination of whether these terms, properly construed, read on the accused process. For the reasons that follow, summary judgment of non-infringement must be granted as to literal infringement of the ’584 patent, but denied as to infringement under the doctrine of equivalents.

I.

The ’584 patent, titled “Process for Tapering Openings in Ternary Glass Coatings,” relates generally to a method for fabricating semiconductor devices, and, more particularly, to a process for forming contoured openings in insulating layers of semiconductor devices. It is the latter process that lies at the heart of the invention claimed in the ’584 patent, and which is central to the disputes at bar. But, to begin with, it is useful as context to describe briefly the typical process steps involved in manufacturing a semiconductor device, at least to the extent those steps are relevant to the ’584 patent.

Semiconductor devices are made by placing successive layers of various materials on a substrate base. During the layering process, particular layers may be removed altogether, or, etched using a template (otherwise known as a mask) to form a pattern, thereby leaving portions in place. This process of layering, removing, and etching is repeated until the desired structure is achieved in the semiconductor material. And, after the desired structure is achieved, but before depositing a first metal layer to connect the semiconductor devices electrically, an insulating, ie. non-eonductive, layer of material is deposited on the semiconductor body. This insulating layer is critical, as it protects the conductive structures of the semiconductor device.

The insulating material, typically a silicon oxide, can be applied by depositing the material on the surface of the semiconductor and then heating the entire device to a sufficient temperature and for a sufficient time to allow the deposited material to flow over the entire surface of the device to create a relatively smooth surface. 2 The temperature required to flow the insulating material depends, in part, on the material’s characteristics. For example, adding various impurities, such as phosphorous, boron, or a combination of both, to the silicon oxide through a process called doping will allow the oxide to flow at lower temperatures than if a pure silicon oxide is used. Moreover, changing the concentrations of boron and phosphorous in the silicon oxide will further affect the temperature at which the insulating material flows. 3 Indeed, the use of a silicon oxide doped with combinations of boron and phosphorous, a substance known as BPSG 4 , is particularly suitable to the semiconductor fabrication process because of the lower temperatures at which this insulating material flows.

After the BPSG insulating layer is applied, contact holes must be cut through the BPSG layer to expose the conductive structures that lie below the insulation. This is accomplished by placing a mask template on the formed BPSG layer, after which contact holes are cut using one of two methods: wet etching or reactive plasma etching. 5 Difficul *824 ties are associated with both methods. If a wet etch is used to cut the contact holes, it is difficult to control the shape and dimensions of the holes. If a reactive plasma etch is used, the walls of the contact holes can be made essentially vertical. Both etching methods can thus result in sharp or abrupt edges that, in turn, cause discontinuities when subsequent layers are deposited. These discontinuities can result in malfunctions, and inoperative devices.

In essence, the ’584 patent discloses a method that alleviates the problems arising from the abrupt edges that result from etching contact holes in the insulating layer. Specifically, the ’584 patent teaches a second heating or partial reflow step, which softens the BPSG after the contact holes are formed. This partial reflow step contours the contact hole edges prior to the deposition of the metal layer, yielding improved metal connection in the contact hole while controlling the hole dimensions. Thus, the method teaches the use of lower temperatures during the partial reflow step to prevent a second full flow of the BPSG, and to prevent the formation of significant, undesirable oxide growth within the contact hole. Such growth might offset any improved contact gains made by the reflow process.

Claim 1 of the ’584 patent, the only claim which is pertinent to the parties’ cross motions 6 , reads, as follows:

1. A process for forming a tapered opening in a glass passivating coating on the surface of a semiconductor body comprising the steps of:

forming a layer of dense, undoped silicon oxide on the semiconductor body;
forming a layer of ternary doped silicon oxide on the undoped layer, the doped layer characterized by having a given flow temperature;
forming a contact opening in both the silicon oxide layers to expose a portion of the semiconductor body; and
heating both oxide layers to a temperature below the given flow temperature of the doped layer for a period of time sufficient to only soften and partially reflow the doped layer at the edges of the contact opening yet insufficient to form a significant oxide growth on the exposed portion of the semiconductor body.

In the instant case, Harris contends that defendant Atmel Corporation, in fabricating several of the accused semiconductor products 7 , infringes the process steps claimed in the ’584 patent. Atmel concedes that the fabrication process in issue 8 , which also involves tapering the contact openings in the BPSG layer of semiconductors, performs the first three steps claimed in the ’584 patent. Thus, the accused Atmel process (i) forms a layer of undoped silicon oxide on the semiconductor body, (ii) forms a layer of ternary doped silicon oxide on the undoped layer, and (iii) forms contact openings in both silicon oxide layers. All that is at issue then is whether the accused process infringes the fourth step claimed in the ’584 patent, the reheating or partial reflow step.

In this regard, Atmel contends that the accused process cannot infringe the ’584 patent because during the partial reflow step, the accused process (1) heats the oxide layers to a temperature above the “given flow temperature,” and (2) creates significant oxide growth in the contact holes. 9

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14 F. Supp. 2d 821, 1998 U.S. Dist. LEXIS 12082, 1998 WL 458236, Counsel Stack Legal Research, https://law.counselstack.com/opinion/harris-corp-v-atmel-corp-vaed-1998.