Cornell University v. Hewlett-Packard Co.

654 F. Supp. 2d 119, 2009 U.S. Dist. LEXIS 37046, 2009 WL 1117389
District Court, N.D. New York·Decided April 24, 2009·No. 01-CV-1974·Published·Cited by 1 cases

Opinion

SECOND AMENDED ORDER

RANDALL R. RADER, Circuit Judge, United States Court of Appeals for the Federal Circuit, sitting by designation.

This court conducted an eight-day jury trial running May 19-30, 2008 to determine the validity and infringement of U.S. Patent No. 4,807,115 (the '115 patent). Finding the '115 patent valid and infringed, the jury awarded damages to Cornell. Hewlett-Packard now moves this court to enter judgment as a matter of law (JMOL) that the '115 is invalid for failure to satisfy the written description requirement, and that Hewlett-Packard did not infringe the patent literally, under the doctrine of equivalents, through inducement, or through contributory infringement. Hewlett-Packard further requests this court to revise the claim construction relied on by the jury and enter JMOL that Hewlett^ Packard did not infringe the '115 patent under that amended claim construction. As an alternative to JMOL, Hewlett-Pack *123 ard requests a new trial on each of these issues. Because the initial claim construction is correct and the jury did not err in finding the '115 patent valid and infringed, this court denies Hewlett-Packard’s motion.

I.

In other orders, this court has described the technology at issue in this case in great detail. Therefore, this order presents only those aspects of the '115 patent pertinent to this motion for JMOL. The '115 patent, entitled “Instruction Issuing Mechanism For Processors With Multiple Functional Units,” issued to Dr. Hwa C. Torng on February 21, 1989. The patent describes technology for issuing multiple and out-of-order computer processor instructions in a single machine clock cycle. This technique employs a dispatch stack and precedence count memory to facilitate multiple and out-of-order processing and enhance the throughput of processors with multiple functional units.

In the computing context, instructions “specify operations a computer is to perform.” Cornell Univ. v. Hewlett-Packard Co., 313 F.Supp.2d 114, 118 (N.D.N.Y.2004) (Markman Order). Importantly, instructions do not employ a universal format. Rather, “[ejach instruction is placed in a certain format, or sequence of fields, each field corresponding to a separate part of the instruction.” Id.

The invention claimed in the '115 patent attempts to remedy a limitation of early computer processors. Historically, processors could only issue and execute one instruction at a time. This limitation derived, in part, from the difficulties posed by dependencies between instructions. Such dependencies arise when one instruction cannot be executed until completion of another. The '115 patent discloses “an instruction issuing mechanism capable of detecting and issuing those instructions which are not dependent and therefore can be performed during the same clock cycle without conflict or error.” Id. at 119.

The '115 patent addresses two categories of dependencies: “essential” and “nonessential” dependencies. Essential dependencies come in just one flavor — “read-after-write” (RAW) dependencies. These RAW dependencies “occur where the result of one operation is needed for the performance of another.” Id. The following two instructions provide an example of a RAW dependency: 1) add A and B, place result in C, and 2) divide C by D, place result in E. The RAW dependency arises because instruction 2) performs an operation on the value resulting from execution of instruction 1). Accordingly, the processor must execute instruction 1) before instruction 2), because instruction 2) depends on instruction 1). Put differently, the processor cannot divide C by D until it computes C by adding A and B together.

Nonessential dependencies, in contrast, come in two flavors — “write-after-read” (WAR) and “write-after-write” (WAW) dependencies. Although the '115 patent addresses both of these nonessential dependency types, only WAR dependencies are relevant to this discussion. Extending the example above, suppose a third instruction is added to the mix: 3) multiply X by Y, place result in C. As is apparent from examining all three instructions, a conflict could potentially arise between instruction 1) and instruction 3) because both write their result to C and instruction 2) uses the value in C in its operation. Thus, if instruction 3) executes after instruction 1) but before instruction 2) the product of X and Y will overwrite the sum of A and B, and instruction 2) will execute using the wrong value, resulting in a WAR error.

The '115 patent addresses RAW, WAR, and WAW dependencies by detecting in *124 structions that are dependency-free — i.e., “concurrencies” — and issuing these dependency-free instructions simultaneously and non-sequentially. The claimed invention achieves this multiple and out-of-order issuance by “enriching” the instruction buffer to make it contain “an additional field or fields to keep track of the dependencies, if any, associated with each source or destination field of the instruction.” Id. at 120. “This enrichment enables the instruction buffer to detect instructions which are free of dependencies and thus ready for execution. The patent refers to the enriched instruction buffer as a ‘dispatch stack.’ ” Id.

The '115 patent describes a single “preferred embodiment” of the claimed invention. That embodiment includes:

(1) a dispatch stack (“DS”), i.e., an “enriched” instruction buffer, which cooperates with a precedence count memory (“PCM”) to detect “concurrently executable (i.e., dependency free) instructions”; and (2) a reservation circuit which then issues these multiple, possibly non-sequential, instructions to the execution unit within a single clock cycle. In the preferred embodiment, the dispatch stack is “enriched” in that it (1) has additional fields and accompanying logic for resolving dependencies in instructions; and (2) stores instructions whose dependency values are “initialized” (i.e., initially as-signed by the PCM). The dispatch stack and PCM eliminate the time-consuming comparison of all the instructions that would otherwise be necessary to ascertain whether the instructions contained dependencies. The preferred embodiment of the present invention is described as operating on a sample set of instructions that have a common instruction format (i.e., OP, SI, S2, D) and contain both essential and false dependencies.

Id. at 122.

Although the preferred embodiment describes a single instruction environment containing both essential and nonessential dependencies, the claims of the '115 patent allow for different instruction sets with different dependency configurations. For example, while independent claims 1, 14, and 15 “broadly teach an invention which detects instructions which are dependency free,” id. at 136, “the dependent claims specify limitations relative to particular instruction formats and particular types of dependencies,” id.

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Cornell University v. Hewlett-Packard Co., 654 F. Supp. 2d 119, 2009 U.S. Dist. LEXIS 37046, 2009 WL 1117389 (N.D.N.Y. 2009).

654 F. Supp. 2d 119 (Cornell University v. Hewlett-Packard Co.) — published by Counsel Stack Legal Research, free access to 12M+ legal documents.

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