OPINION
CALEB M. WRIGHT, Senior District Judge.
Plaintiff, Bell Telephone Laboratories, Inc. (“BTL”), seeks relief under 35 U.S.C. § 291
against defendants Hughes Aircraft Co. (“Hughes”) and General Instruments Corp. (“G.I.”). BTL alleges that an interference exists between its United States Letters Patent Number 3,475,234 (the Kerwin patent), and United States Letters Patent Numbers 3,544,399 (the Dill patent) and 3,576,478 (the Watkins patent), owned by Hughes and G.I. respectively. BTL seeks an adjudication of that interference and a declaration that it is the sole owner of the patent rights in interference.
This Court has jurisdiction under 28 U.S.C. § 1338(a). Since plaintiff, BTL, is a New York corporation and both defendants are Delaware corporations venue is proper under 28 U.S.C. § 1391(c).
Cf., Standard Oil Co. v. Montecatini Edison, S.p.A.,
342 F.Supp. 124 (D.Del.1972).
Previously this Court has entertained a suit in which Hughes charged General Instruments with infringement of the Dill patent. General Instruments defended on the grounds,
inter alia,
that the Dill patent was invalid by reason of Watkins’ prior invention. After separate trial on this priority issue, this Court held that although Watkins had conceived the invention in March of 1965, Watkins did not reduce the invention to practice until the filing of a patent application on November 17, 1966. Dill, however, was found to have conceived on May 1, 1966, and to have reduced to practice constructively by the filing of a patent application on October 26, 1966. Since Watkins was the first to conceive but the last to reduce to practice, his diligence from Dill’s conception until his own filing was necessary to a finding that he was the prior inventor. No such diligence was found and Hughes prevailed.
See Hughes Aircraft Co. v. General Instruments Corp.,
374 F.Supp. 1166 (D.Del.1974). Before further proceedings on the remaining validity and infringement issues in that case occurred, the present suit was filed by BTL.
At an early stage in these proceedings, Hughes moved for dismissal on the ground that no interference existed. This Court was unwilling to hold on the record then extant that the patents were non-interfer
ing. Accordingly that motion was denied. 185 U.S.P.Q. 660. G.I. participated in the briefing of that motion and urged that a three-way interference existed. However, as a result of a settlement agreement with Hughes, G.I. ceased participating in these proceedings prior to the argument on the Hughes’ motion.
See
185 U.S.P.Q. at 661.
Following denial of the dismissal motion, Hughes dropped its position that the Kerwin and Dill patents were non-interfering and the case proceeded to trial on the merits. The matter is now ready for decision.
The purpose of a suit under 35 U.S.C. § 291 is to establish priority of invention as between patentees. Priority is determined by the standard found in 35 U.S.C. § 102(g):
In determining priority of invention, there shall be considered not only the respective dates of conception and reduction to practice of the invention, but also the reasonable diligence of one who was first to conceive and last to reduce to practice, from a time prior to conception by the other.
In the instant suit, the parties have stipulated to the Hughes dates determined by this Court in the
Hughes v. General Instrument
infringement action.
The parties therefore presented this Court with proofs only respecting BTL’s dates of conception and reduction to practice. In the event that the Court were to determine that the Kerwin invention was conceived prior to May, 1966, and reduced to practice after October 26, 1966, BTL also sought to show that the Kerwin inventors exercised diligence from prior to May 1966 until such time as they had achieved a reduction to practice.
The invention in the priority contest is directed to a semi-conductor device known as a “silicon-gate field effect transistor”. (“S.G.F.E.T.”). A field effect transistor (“F.E.T.”) is a three-electrode electronic amplifier formed in a small semi-conductor. The semi-conductor is usually silicon and is referred to as a “slice”, “chip”, or “wafer”. The three electrodes are known as the “source”, “drain”, and “gate”. The source and the drain electrodes are formed in the silicon wafer by “doping” selected portions of the wafer with selected impurities. The area separating the source and drain is known as the “channel”, and normally will resist the flow of current. However, in an F.E.T., the channel is overlayed with an insulating layer, and the gate electrode is formed on top of that layer. When an appropriate voltage is applied to this gate, current is able to flow along the previously resistant path between the source and drain. Further, variations in the voltage applied to the gate will result in variations in the current flowing between the source and drain.
Prior to the development of the invention in suit, a major problem in fabricating these devices was the positioning (or alignment) of the gate electrode. The devices are of very small dimensions and it was desirable to make them even smaller. It accordingly was very difficult to align precisely a strip of metal (usually aluminum) on top of the insulator which overlaid the channel separating the source and drain.
The S.G.F.E.T. avoided this alignment problem completely by virtue of its so-called “self-alignment” feature. To effect self-alignment, a silicon layer is positioned over the insulating layer covering the channel on the chip prior to forming the source and drain regions. The doping or diffusion
step which results in formation of the source and drain is then performed. The silicon acts as a “mask” during this step and prevents doping of the channel region. The source and drain are thus formed precisely at the edges of the silicon gate, and the gate itself becomes sufficiently doped to become a conductor and thus act as an electrode.
This sequence, performing the diffusion step after placement of the gate electrode, had been impossible using the prior art, for the metal gates, usually aluminum, would melt at the temperatures required for diffusion.
The Work At Bell Telephone Laboratories.
Work on a S.G.F.E.T. by the Kerwin
group can be traced to a meeting held at BTL in February, 1966. The meeting was called by Donald Klein, and was attended by members of his research group, as well as by other BTL technical personnel. Kerwin and Sarace were among those attending the meeting. (T-49, 278, 680),
The purpose of the meeting was to discuss problems which arose in making integrated circuits composed of large numbers of solid state devices. A significant problem respecting “yields” was always present in the manufacture of the circuits in a multi-step process. Even when each step in a process was highly efficient and resulted individually in a high yield, after a sequence of many such steps had been performed on a given device array, the percentage of operative devices in the array would be unsatisfactorily low. To overcome this problem, Klein hoped that his group would be able to come up with a so-called “go, no-go” sequence of device fabrication steps. A sequence of “go, no-go” process steps could approach 100% efficiency for it envisaged the use of materials which either would or would not be subject to reaction in a given chemical process step. (T — 45-47; 49-50).
During the course of this meeting, at which a variety of potential process steps were discussed, Kerwin came to the key realization that placement of a thermally resistant gate prior to doping of the source and drain regions would eliminate the problems encountered in aligning the gate electrode. (T-280-85). Silicon, a material with which the group had experience, was the thermally resistant material chosen. (T-286). The S.G.F.E.T. fabrication process which resulted from this meeting was recorded by Klein (PX-10). Somewhat later, in early March, following discussion between Klein and his superior Hugh M. Cleveland, the latter developed a chart detailing the work assignments that would be involved in carrying out the project. (PX-15; T-576-77). In summary, the fabrication sequence involved the following steps:
1. Preparation of a silicon chip. This step, while rather involved and time consuming, is only the preparation of starting materials. It does not relate directly to the invention.
2. Deposition of an insulating layer on the upper surface of the chip. The parties disagree on which insulating materials were initially embraced by the Kerwin group. Without question, silicon nitride was the insulator of choice by those at the February meeting. The contemporaneous evidence, however, convinces this Court that silicon nitride was not the only insulator considered. Reference to silicon nitride was somewhat equivocable, e. g., Klein’s notes (PX-10) in reference to this insulating layer, contains the notation “(SÍ3N4?)” and Cleveland’s notes (PX-15) expressly indicate that an alternative to silicon nitride was considered. This alternative insulator
was a layer of silicon oxide over the silicon, followed by a layer of silicon nitride. This two layer insulating medium is referred to as a “sandwich”.
See
Fig. 1, Appendix.
3. Deposition of a layer of silicon oxide on top of the insulating layer. See Fig. 2, Appendix.
4. The selective etching away of the silicon oxide layer from the surface of the chip. This etching was to be effectuated by a so-called photoresist technique. The photoresist technique is used to place a plastic film over a portion of the surface of the device.
The plastic film then functions as an etch mask for the subsequent removal of undesired portions of the underlying silicon oxide layer.
See
Fig. 3(A), Appendix. This is possible because certain agents which will dissolve silicon oxide, e. g., ammonium bi-fluoride, will be unreactive to the plastic film. Further, the ammonium bifluoride will have little effect on the underlying silicon nitride layer — thus in the jargon of the BTL group, the etch process would be “go, no-go” — go as to the silicon oxide and no-go as to the silicon nitride.
The remaining portions of the photoresist material are then removed.
See
Fig. 3(B), Appendix.
5. Deposition of a silicon layer across the entire surface.
See
Fig. 4, Appendix.
6. Placement of a plastic film by photo-resist procedure over selected portions of the silicon layer, followed by etching away of a portion of the silicon layer with a mixture of hydrofluoric, nitric and acetic acids saturated with iodine. This mixture has little effect on the layers underlying the silicon. Subsequently the plastic film is removed by suitable solvent.
See
Fig. 5, Appendix.
7. Removal of exposed silicon oxide by use of ammonium bifluoride which will remove exposed SÍO2 but have little effect on silicon or silicon nitride.
See
Fig. 6, Appendix.
8. Removal of the silicon nitride layer by use of hot phosphoric acid, a solvent to which the underlying silicon or, in the case of the sandwich, silicon oxide, is impervious. In the case of the sandwich, underlying silicon oxide must then also be removed, again using ammonium bifluoride. In these etch steps, the silicon gate functions as an etch mask over the underlying insulator. These etch steps are followed by the diffusion or “doping” step, which results in formation of the source and drain electrodes. During this latter procedure, the silicon gate acts as a diffusion mask.
See
Fig. 7.
9. Metallization. This step involves placement of metal on the electrode surface. This is required in order to facilitate attachment of wires to the device.
Following the February meeting, BTL investigators immediately began to try to produce field effect transistors using the newly devised fabrication sequence. Many of the individual steps in the process, however, were time-consuming, though routine. Accordingly, the first semi-completed devices were not tested until late May or early June of 1966. The devices which were then tested employed a single silicon nitride layer, and not the sandwich, as a gate insulator. Further, these devices were not “metallized”. That is, the devices did not have metal covering the electrode surfaces for the attachment of wire leads. Accordingly, the devices were tested using a so-called probe test.
A probe test involves the physical placement of wires against the electrode surfaces — the physical placement being facilitated by holding the device array in a clamp and moving wire probes with a micrometer-like screw down on to the appropriate surface locations. The operator, performing
the test peers through a microscope while making contact to ascertain that the wires are being held against the desired electrode. (T-194-99).
The late May-early June probe tests of the nitride devices were clearly successful. The tests showed a “transistor effect”, i. e., they showed drain-to-source current as a function of drain-to-source voltage for different applied gate voltages, which curves were within a commercially accepted range; and the tests showed this result was true for a high proportion of the devices tested. (PX-24).
After the probe tests were performed, Sarace attempted to metallize the devices. The conventional procedure would have been to use a so-called “aluminization” process. The parties agree that such a process would have been routine and its effectuation would have been within the purview of one of ordinary skill in the art.
Sarace, however, elected to perform a “platinization” procedure.
This procedure was somewhat experimental but was also a more rapid and convenient procedure. (T-81, 151).
Unfortunately for Sarace, the platinization procedure, which was performed in late June 1966, produced only “shorted” devices. (PX-16 at 56; T-741-42).
Up until this time, work on the silicon gate project had required the efforts of several individuals. From this time on, however, Sarace was the only BTL employee to be assigned essentially full time to the project. (T-703, 732, 788). Following the failure with platinization, Sarace did not immediately switch to a conventional metallization procedure. Rather, he performed a microscopic examination of the shorted device in an effort to determine the source of the shorts. This examination failed to reveal the source of the shorts, but it did disclose an over-etching step. (PX-16 at 56). Although this over-etching had apparently not been exemplified in prior tests of the electrical characteristics of the devices, Sarace proceeded with a series of tests aimed at developing more precise etching-step parameters. This phase of Sarace’s work continued into August of 1966. In addition, Sarace worked on several other problems affecting the devices.
During the course of his work on these problems, Sarace became aware of a further problem, a hysterisis effect on the devices having a silicon-to-silicon nitride interface.
Hysterisis can be considered a type of electrical instability.
While hysterisis did not make these devices totally unsatisfac
tory, it was a deficiency which it was desirable to overcome. Accordingly, Sarace directed his efforts to overcoming the hysterisis problem. A solution to the hysterisis problem was somewhat elusive. Sarace’s notebook (PX-16) indicates that up until October 17, 1966 no solution to the hysterisis problem had been found.
There are no entries from October 17, 1966 until January 17, 1967 in the laboratory notebook of Sarace, the only BTL employee then devoting full time to the S.G.F. E.T. project. The activities at BTL during this period are not recorded on a day-to-day basis and, therefore, must be gleaned from (1) the testimony of Sarace and others;
and (2) certain other supporting documents. The earliest dated documents showing a solution to the hysterisis problem are in form of viewgraph slides (PX-42) which were prepared in conjunction with a talk that Sarace gave at a meeting with another group of BTL workers in Allentown, Pennsylvania. This meeting was held December 9, 1966 (T-793), and the viewgraphs were presumably prepared shortly before that date. These viewgraph slides show that sometime prior to December 9, Sarace had employed the so-called “sandwich” construction and that this construction had resulted in elimination of the hysterisis problem.
Another document which supports a November date of completion for a S.G.F.E.T. utilizing the sandwich construction is a memorandum dated January 5, 1967 (PX-48) sent from Mr. Biondi, the director of the electron device laboratory, to Mr. Cave of the BTL Patent Department. Although the memorandum is over Mr. Biondi’s signature, it was actually written by Kerwin. (T-326). This memorandum indicates that subsequent to a prior memorandum dated November 15, 1966 (PX-35), the “sandwich” process was employed; that the sandwich process improved electrical stability; and that sandwich-containing devices were undergoing life tests.
In life tests, the devices are subject to stress conditions, e. g., elevated temperatures, and periodically data is gathered from the devices to check for changing electrical characteristics; that is, the devices are placed in a furnace and removed at given intervals for electrical testing, then returned to the furnace for a further time interval. These life tests are used to indicate the “stability” and “reliability” of the devices. (T-152, 321-22). Also they would show whether a device would “last long enough to be useful”. (T-231). These tests required, as a practical matter, that the devices first be metallized. (T-152, 714).
Not until January 1967 did the Patent Department at BTL commence preparation of a patent application directed to the Kerwin invention. The application was filed March 27, 1967.
The Existence Of An Interference.
Although Hughes at one time acceded to BTL’s position that an interference existed, the Court expressed reluctance to accept a stipulation on this question. Since the question of whether an interference exists may, in a § 291 suit, be characterized as going to the Court’s subject matter jurisdiction, the Court deemed it inappropriate for the parties to stipulate to the matter. The Court asked the parties to address themselves anew to the question of the existence of an interference in their post-trial briefs.
Hughes again contends that no interference exists, but the Court is of the view that the evidence in the record unequivocally supports the existence of an interference. As this Court noted in denying Hughes’ dismissal motion, the allegedly interfering claims of the Dill and the Kerwin patents differ in only one respect — the process claimed in the Dill patent recites a step of “etching away the exposed portions
of said insulating layer”, while the corresponding step in the Kerwin patent reads “etching away the exposed portions of said insulating layer
using said silicon layer as a mask”,
(emphasis added). See 185 U.S.P.Q. at 661.
However, in Dill’s original Invention Disclosure which he submitted to the Hughes’ Patent Department, he referred to the use of the “Si layer as a mask”. (Pretrial Order ¶ 27). Further, the parties agree that Dill correctly testified before this Court in the
Hughes
v.
General Instruments
trial that his invention did not require a separate masking step and that those skilled in the art would recognize that the silicon gate itself acted as an etch mask. (Pretrial Order ¶ 33). Thus, this Court is satisfied that Claim 1 of the BTL patent and Claim 5 of the Hughes patent are, in fact, interfering.
After trial, Hughes advanced two additional arguments in support of the view that the patents were not interfering. First, Hughes contended that if the Dill process were modified to include the deposition of metal on top of the silicon gate, then that metal, and not the silicon, would act as an etch mask. There is no testimony or suggestion in the record, however, that indicates the Dill process has never been so practiced. Further, it is not evident to this Court that even if the process were so practiced that the metal would perform as the mask to the exclusion of the underlying silicon. Second, Hughes contended that the use of silicon as an etch mask in the Kerwin process refers to the use of silicon as a mask for the field oxide layer, which layer is lacking in the Dill process. Again, since the issue was raised after trial, the Court has no testimony in support of this view. However, as this Court understands the Kerwin process, the fact that silicon may act as an etch mask for the field oxide does not diminish the fact that the silicon gate also inevitably serves as an etch mask with respect to the gate insulator. Accordingly, the Court finds that an interference for purposes of § 291 does, in fact, exist.
Conception.
A “conception is the mental part of the process in arriving at invention”.
Electro-Metallurgical Co. v. Krupp Nirosta Co.,
122 F.2d 314, 318 (3rd Cir. 1941). Conception is not, however, merely “the perception or realization of the desirability of producing a certain result; rather it is the perception or realization of the means by which the result can be produced.” 1 Rivise and Caesar, Interference Law and Practice § 110 (1940). Further, this mental possession of the means must be such that completion or effectuation of the invention requires no more than routine skill. Accordingly, the need for extensive subsequent research will negate an earlier asserted date of conception.
See Alpert
v.
Slatin,
305 F.2d 891, 894 (C.C.P.A.1962). It is clear that at their February 1966 meeting, the BTL group did more than merely recognize a problem. Hughes argues, however, that the February conception was incomplete in that extensive research was required to reduce the February conception to practice. The BTL inventors acknowledged that at the time of the February meeting, they were uncertain of their ability to carry out certain of the process steps envisaged in their conception.
See, e. g.,
T-287. Viewing the events after the fact, however, this Court is convinced that BTL inventors faced no problems in pursing a reduction to practice which required the use of inventive skill. That is, while it was impossible in February 1966 to state with certainty that the BTL process would work, events would show that the process did work. Further, while the process of reducing the invention to practice was lengthy, this was not primarily the result of extensive experimentation required for a successful reduction to practice. Many of the individual process steps, though old in the art, were quite time consuming. Further, much of the experimentation was directed to solving the hysterisis problem, a problem which in itself would not have precluded a successful reduction to practice.
Accordingly, this
Court is convinced that BTL has met its burden of proof
respecting its entitlement to a February-March conception date.
Reduction To Practice.
“A process is said to be reduced to practice when the series of steps constituting the process are carried out in such a manner as to demonstrate the practicability of the process.” Rivise & Caesar,
supra,
§ 131 (citing
Corona Cord Tire Co. v. Dovan Chemical Corp.,
276 U.S. 358, 48 S.Ct. 380, 72 L.Ed. 610 (1928)). Further, in the case of a product-producing process, a reduction to practice requires the establishment of utility for the products produced by the process.
See, e. g., Tennessee Valley Authority v. Monsanto Chemical Co.,
383 F.2d 973, 977 (5th Cir. 1957). Accordingly, the date of BTL’s reduction to practice is the date on which BTL can show that it produced a useful field-effect transistor using the silicon gate process.
BTL contends that such a reduction to practice was shown by the probe tests in the period of late May to early June 1966. Hughes contends that the probe tests involved less than completed devices and, as such, they were insufficient to demonstrate a reduction to practice.
There are a multiplicity of opinions dealing with the question of whether or not a given laboratory or bench test constitutes a reduction to practice in a particular case.
See, e. g.,
Rivise & Caesar,
supra,
§ 143 and § 144. The frequently stated rule is that “a test under service conditions is necessary in those cases, and in those only, in which persons qualified in the art would require such a test before they are willing to manufacture and sell the invention, as it stands.”
Sinko Tool & Manufacturing Co. v. Automatic Devices Corp.,
157 F.2d 974, 977 (2d Cir. 1946).
While this Court is convinced that the May-June 1966 probe tests constituted a successful intermediate experiment, BTL has failed to establish that those tests demonstrated that the devices possessed the utility required for a reduction to practice. The testimony of BTL’s own inventors was that life tests of completed devices were necessary in order to demonstrate that the devices were reliable and useful.
These life tests establishing a reduction to practice were not completed until December 1966-January 1967.
Diligence.
Since BTL has established a date of conception prior to Dill’s date of conception but has established a date of reduction to practice subsequent to Dill’s date of reduction to practice, BTL can prevail only if the Kerwin group is found to have exercised reasonable diligence from just prior to Dill’s conception up until their reduction to practice in December 1966-January 1967.
“The party chargeable with diligence must account for the entire period during which diligence is required.”
Gould v. Schawlow,
363 F.2d 908, 919 (C.C.P.A.1966). Further, in making such account, the testimony of the inventor alone is usually deemed insufficient.
Id.
at 919;
Slet
zinger v. Lincoln,
410 F.2d 808, 812 (C.C.P.A.1969).
There is no question that the Kerwin inventors were diligent from the time of their February-March 1966 conception up until the time of the probe tests in May-June 1966. In the second half of 1966, however, Sarace was the only inventor devoting full time to the project and his records show a substantial void, from October 17, 1966 until January 17, 1967. Sarace testified that it was in this period that he returned to the “sandwich” conception, and constructed and tested such a device, though his notes do not reflect this. However, certain other evidence does corroborate Sarace’s testimony of full-time efforts on the S.G.F.E.T.
On December 9, Sarace presented view-graphs with test data from sandwich devices to a meeting at Allentown, and this indicates that BTL workers had completed fabrication of these devices by late November 1966.
Further, the January 5, 1967 Biondi memorandum (PX^48) indicates that the time-consuming life tests were then underway.
While a day-to-day corroboration of Sarace’s testimony regarding his activity during the fall of 1966 would be desirable, this Court concludes that its absence is not fatal to BTL’s case. It is sufficient that BTL has established by competent evidence an inference more reasonable than not that work on the silicon gate process continued uninterrupted from prior to Dill’s date of conception until completion of the life tests which constituted a reduction to practice. The Court thus finds that BTL has met its burden of proof regarding the exercise of reasonable diligence.
Accordingly, BTL is declared to be prior inventor of that subject matter common to the Dill and Kerwin patents.
Submit order.
APPENDIX
Schematic representation of (A), silicon (Si) chip on which a silicon nitride (Si3N4) layer has been deposited and (B), silicon chip on which a silicon oxide (Si02) layer has first been deposited, followed by a silicon nitride layer. Figure IB represents the so-called sandwich construction. It is that construction which is depicted in all of the following figures.
Schematic representation of device following completion of step 3.
Schematic representation of (A) device following photoresist step and (B) device following etching of Si02 and removal of photoresist.
Schematic representation of device following step 5.
Schematic representation of device following step 6.
Schematic representation of device following step 7.
Schematic representation of device following step 8.