Rozbicki v. Chiang

590 F. App'x 990
CourtCourt of Appeals for the Federal Circuit
DecidedNovember 14, 2014
Docket2014-1041
StatusUnpublished
Cited by1 cases

This text of 590 F. App'x 990 (Rozbicki v. Chiang) is published on Counsel Stack Legal Research, covering Court of Appeals for the Federal Circuit primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Rozbicki v. Chiang, 590 F. App'x 990 (Fed. Cir. 2014).

Opinion

O’MALLEY, Circuit Judge.

This patent appeal arises from an interference proceeding before the United States Patent and Trademark Office Patent Trial and Appeal Board (“PTAB”) relating to technology for depositing and etching barrier materials on wafer substrates. The PTAB construed the term “etching” as “the removal of material to create a pattern.” Relying on this construction, the PTAB found that U.S. Patent Application No. 11/733,671 (“the Chiang Application”) contained adequate written description support for the lone interference count.

On appeal, Rozbicki challenges the PTAB’s construction of “etching” and its written description finding. Because we agree with the PTAB’s claim construction, we affirm its written description decision for Chiang claims 31-39, 46, 59-61, 63, 64, 66-71, 83, and 84 as it is supported by substantial evidence. We vacate and remand the PTAB’s decision for Chiang claims 47, 49, 51, 53, 55, 57, 76-82, 85, 87, 88, and 90, however, because we find that the PTAB’s explanation of how the Chiang Application describes the “net etching” limitation is inadequate.

BACKGROUND

This technology relates to wafer substrates to make integrated circuits. The wafer substrates contain semiconductor devices that are electrically connected to form the integrated circuits. Appellee Br. 4. These electrical connections are made using vias, which are openings in a layer of silicon dioxide above the wafer substrate. Id. These vias are filled with metal to make the electrical connections. Id. Previously, semiconductor manufacturers used aluminum to make these electrical connections. Id. Eventually, manufacturers switched to copper, which has a lower resistivity. Id. This switch, however, required the placement of a layer of barrier material between the silicon dioxide and the copper to prevent the copper from diffusing into the silicon dioxide. Id. Normally, this barrier material is placed over the silicon dioxide through a physical vapor deposition process, such as, sputtering or a chemical vapor deposition process. '977 Patent col. 2 11. 13-16. Sputtering is a process where atoms are ejected from a solid target material towards a substrate by bombarding the target material with energetic particles. Resputtering is the sputtering of previously deposited material. Typical barrier materials can include tantalum, tantalum nitride, tungsten, titanium, titanium tungsten, titanium nitride, etc. '977 Patent col. 2 11. 11-13. The identical claims-at-issue on appeal from both disclosures are directed to a method of depositing barrier material.

*992 U.S. Patent No. 6,607,977 (“the '977 Patent” or “the Rozbicki Patent”) issued on August 19, 2003. It is titled “Method of Depositing a Diffusion Barrier for Copper Interconnect Applications.” '977 Patent, at [54] (filed September 26, 2001). As shown in Figure SC below, the invention discloses a first step of depositing barrier material 325 to provide coverage, then a second step of depositing additional barrier material and simultaneously etching a portion of the barrier material deposited in the first step as seen in Figure 3D.

[[Image here]]

'977 Patent Fig. 3C, 3D. The summary of the invention states that the result of the steps is a metal diffusion barrier formed in part by “net etching” in the bottom of the vias and “net deposition” on the side walls. The specification describes “net etching” as having an “etch to deposition ratio” or “E/D” that is greater than 1. The purpose of this “net etching” is to reduce the resistance of subsequently formed metal interconnects.

The Chiang Application relates to “a method of sputtering a sculptured coating over the walls of a high aspect ratio semiconductor feature in a manner which avoids or significantly reduces the possibility of damage to or contamination of underlying surfaces.” Joint Appendix (“J.A.”) 1180. The Chiang Application generally describes applying a first portion of a sculptured layer using traditional sputtering or ion deposition sputtering with a low substrate bias such that a surface onto which said sculptured layer is applied is not eroded away. J.A. 1188. It then describes applying a subsequent portion of the sculptured layer using ion deposition sputtering with sufficiently high substrate bias to sculpture a shape from said first portion while depositing additional layer material. J.A. 1188. Chiang .explains that, “[a]fter deposition of a first portion of barrier layer material, the bias voltage is increased during the deposition of additional barrier layer material over the feature surface. The application of increased bias voltage results in the res-puttering (sculpturing) of the first portion of barrier layer or wetting layer material (deposited at the lower substrate bias voltage) while enabling a more anisotropic deposition of newly depositing material.” J.A. 1190. “Availability of the material which was deposited at the lower bias voltage on the surface of a trench or via protects the substrate surface under the barrier or wetting layer material during the sputtering deposition at higher bias voltage. This avoids breakthrough into the substrate by impacting ionized material which could destroy device functionality.” J.A. 1190.

*993 Chiang provides three examples in his application, which correspond to the Chiang Application Figures 3 to 5. The key example is Example B, describing Figure 5.

This figure discloses an embodiment involving an initial deposition where a barrier material is applied for 15 seconds without the application of substrate biasing power, then applying a substrate biasing power of -60V (250W) while depositing barrier material through ion deposition plasma for about 45 seconds. J.A. 1200-01. During this second deposition period, barrier material from the first deposition period is resputtered, with excess barrier material being removed and reshaped. J.A. 1201.

On May 25, 2012, the PTAJB declared Interference No. 105,898 between claims 1-73 of the Rozbicki Patent and claims 31-90 of the Chiang Application. As Chiang copied its claim language from the Roz-bicki Patent, the interference included a single count: claim 1 of the '977 Patent which is the same as claim 31 of the Chiang Application. These identical claims state:

A method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a wafer substrate, the method comprising:
(a) depositing a first portion of the diffusion barrier over the surface of the wafer substrate;
(b) etching the first portion of the diffusion barrier at the bottom of a plurality of vias without fully etching through such that an amount of barrier material remains at the bottom of the plurality of vias, while depositing a second portion of the diffusion barrier elsewhere on the wafer substrate; and
(c) depositing the metal conductive layer over the surface of the wafer substrate such that the metal conductive layer contacts the barrier material remaining at the bottom of the plurality of vias; wherein at least part of (a) and all of (b) are performed in the same processing chamber.

J.A.

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Bluebook (online)
590 F. App'x 990, Counsel Stack Legal Research, https://law.counselstack.com/opinion/rozbicki-v-chiang-cafc-2014.