Robert N. Noyce v. Jack St. Clair Kilby, Jack St. Clair Kilby v. Robert N. Noyce

416 F.2d 1391, 57 C.C.P.A. 1156
CourtCourt of Customs and Patent Appeals
DecidedJanuary 29, 1970
DocketPatent Appeal 8182, 8205
StatusPublished
Cited by7 cases

This text of 416 F.2d 1391 (Robert N. Noyce v. Jack St. Clair Kilby, Jack St. Clair Kilby v. Robert N. Noyce) is published on Counsel Stack Legal Research, covering Court of Customs and Patent Appeals primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Robert N. Noyce v. Jack St. Clair Kilby, Jack St. Clair Kilby v. Robert N. Noyce, 416 F.2d 1391, 57 C.C.P.A. 1156 (ccpa 1970).

Opinion

ALMOND, Judge.

These are cross-appeals from the decision of the Board of Patent Interferences awarding priority of invention as to counts 1-4 to Kilby and counts 5 and 6 to Noyce in Interference No. 92,841 involving Noyce patent No. 2,981,877, issued April 25, 1961 on an application 1 filed July 80, 1959, and Kilby application serial No. 169,557, filed January 29, 1962.

The sole issue is whether counts 1-4, the subject matter of No. 8182 taken by Noyce, and count 6, 2 involved in No. 8205 brought by Kilby, are supported by a prior eopending application of Kilby, serial No. 791,602, filed February 6, 1959 (hereinafter the '602 application). 3 For reasons hereinafter stated, we find that the counts in issue are not supported by the '602 application, and therefore reverse the decision of the board as to counts 1-4 in No. 8182 and affirm it as to count C in No. 8205.

The subject matter in issue is a semiconductor device including an electrical lead or connection thereto, which device is suitable for use in integrated electronic *1392 circuits of very small size. 4 Count 1 is representative:

1. A semiconductor device comprising a body of semiconductor having a surface, said body containing adjacent P-type and N-type regions with a junction therebetween extending to said surface, two closely spaced contacts a [sic] adherent to said surface upon opposite sides of and adjacent to one portion of said junction, an insulating layer consisting essentially of oxide of said semiconductor on and adherent to said surface, said' layer extending across a different portion of said junction, and an electrical connection to one of said contacts comprising a conductor adherent to said layer, said conductor extending from said one contact over said layer across said different portion of the junction, thereby providing electrical connections to both of the closely spaced contacts.

A multi-device semiconductor and lead structure embodying the invention is shown in Figs. 3 and 4 of the Noyce patent, plan and sectional elevation, respectively, as follows:

*1393 The illustrated device includes a semiconductor body 11 of silicon of the P-type with one side having a surface 12 and the other side plated with a metal coating 13 which serves as an electrical contact. A plurality of circuit elements are formed within and on the body of silicon by diffusing N-type and P-type dopants, restricted to specific areas by known masking techniques, through the surface 12 to form a plurality of N-type and P-type semiconductor regions which are separated from the underlying P-type region and from each other by a plurality of disked, P-N junctions of various diameters and depths.

Toward the left end of the structure illustrated in Figs. 3 and 4 is shown an N-type region overlying a small P-type region and separated therefrom by a disked junction 14. The small P-type region overlies another N-type region, and the latter N-type region in turn overlies the large P-type region comprising the bulk of the body and is separated therefrom by a disked junction 15. A discoid metal contact 16, adherent to surface 12 within junction 14, makes electrical connection to the upper N-type region. Electrical connection to the two regions between junctions 14 and 15 is made through a C-shaped metal contact 17 adherent to those regions. Since the two intermediate regions of semiconductor material are electrically interconnected by the contact 17, the resulting structure comprises two rectifying P-N junctions in series circuit.

Except for the contacts 16 and 17 and the contacts for other semiconductor devices shown to the right of the device just described, the entire surface 12 is covered with an insulating layer of oxidized silicon. That insulating layer may be formed upon the exposed surface of the silicon during the diffusion of the dopants into the silicon and the contact areas subsequently cleared of the layer by photoengraving techniques. Afterward, conductive metal such as aluminum may be deposited by vacuum deposition and photo-engraving procedures may be used subsequently to remove all the deposited metal except that forming the contacts, such as 16 and 17, and electrical connecting leads thereto such as are shown at 28 and 30. Thus the metal lead strip 30 constituting the conductor from contact 16 passes over junctions 14 and 15 in insulated relationship thereto as the result of intervening oxide layer 27. The Noyce specification emphasizes throughout that the lead strips or conductors are adherent to the oxide layer.

The conductor 30 similarly passes in insulated relationship over another junction 18 of a semiconductor device designed to serve as a capacitor to make electrical connection to terminal 19 of that device. Additional semiconductor devices shown iii the drawing include a transistor.

The disclosure of Kilby application '602 is best considered in connection with Fig. 6a thereof:

A thin wafer of single-crystal semiconductor material containing a diffused P-N junction shown there has been processed and shaped to form an integrated *1394 electronic circuit constituting a multivibrator. Among the elements of the circuit are resistors Ri, R2 and R3 and capacitors Ci and C2. Also formed are mesa transistors 5 Ti and T2. Although a semiconducting wafer that is “preferably silicon or germanium” is mentioned, P-type germanium is said to be used for the device shown. In producing the device, one side of the wafer is lapped and polished and then subjected to an antimony diffusion process to provide an N-type layer. Gold is evaporated through a mask to produce areas 51 to 54 which provide ohmic contact 6 with the N-type region such as the transistor base connections. Aluminum is evaporated through a mask shaped to provide the transistor emitter areas 56, which areas form rectifying contacts with the N-type layer. After utilizing a photosensitive resist process to etch the wafer to the proper shape, the photoresist is removed by a solvent and mesa areas 60 are masked by the same photographic process, and the wafer is again etched and the N-type layer removed in the exposed areas. Gold wires 70 are then thermally bonded to appropriate areas to make the necessary electrical connections. As examples, one wire 70 interconnects the emitter areas 56 of the two transistors Ti and T2 and base areas of the transistors are connected to contacts 51 and 52, respectively.

Kilby’s Fig. 6a embodiment shows the gold connecting wires 70 insulated from the other circuit components and from each other by reason of their extending upwardly from the wafer into the air. However, the application describes a modification in a partial paragraph thereof as follows:

Instead of using the gold wires 70, in making electrical connections, connections may be provided in other ways.

Free access — add to your briefcase to read the full text and ask questions with AI

Related

Cite This Page — Counsel Stack

Bluebook (online)
416 F.2d 1391, 57 C.C.P.A. 1156, Counsel Stack Legal Research, https://law.counselstack.com/opinion/robert-n-noyce-v-jack-st-clair-kilby-jack-st-clair-kilby-v-robert-n-ccpa-1970.