Rambus Inc. v. Federal Trade Commission

522 F.3d 456, 380 U.S. App. D.C. 431, 86 U.S.P.Q. 2d (BNA) 1539, 2008 U.S. App. LEXIS 8662
CourtCourt of Appeals for the D.C. Circuit
DecidedApril 22, 2008
Docket07-1086, 07-1124
StatusPublished
Cited by10 cases

This text of 522 F.3d 456 (Rambus Inc. v. Federal Trade Commission) is published on Counsel Stack Legal Research, covering Court of Appeals for the D.C. Circuit primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Rambus Inc. v. Federal Trade Commission, 522 F.3d 456, 380 U.S. App. D.C. 431, 86 U.S.P.Q. 2d (BNA) 1539, 2008 U.S. App. LEXIS 8662 (D.C. Cir. 2008).

Opinion

Opinion for the Court filed by Senior Circuit Judge WILLIAMS.

WILLIAMS, Senior Circuit Judge:

Rambus Inc. develops computer memory technologies, secures intellectual property *459 rights over them, and then licenses them to manufacturers in exchange for royalty payments. In 1990, Rambus’s founders filed a patent application claiming the invention of a faster architecture for dynamic random access memory (“DRAM”). In recent years, Rambus has asserted that patents issued to protect its invention cover four technologies that a private standard-setting organization (“SSO”) included in DRAM industry standards.

Before an SSO adopts a standard, there is often vigorous competition among different technologies for incorporation into that standard. After standardization, however, the dynamic typically shifts, as industry members begin adhering to the standard and the standardized features start to dominate. In this case, 90% of DRAM production is compliant with the standards at issue, and therefore the technologies adopted in those standards — including those over which Rambus claims patent rights — enjoy a similar level of dominance over their alternatives.

After lengthy proceedings, the Federal Trade Commission determined that Ram-bus, while participating in the standard-setting process, deceptively failed to disclose to the SSO the patent interests it held in four technologies that were standardized. Those interests ranged from issued patents, to pending patent applications, to plans to amend those patent applications to add new claims; Rambus’s patent rights in all these interests are said to be sufficiently connected to the invention described in Rambus’s original 1990 application that its rights would relate back to its date. Commission Br. at 46-47; Transcript of Oral Argument at 35-36; see also 35 U.S.C. §§ 120, 132. Finding this conduct monopolistic and in violation of § 2 of the Sherman Act, 15 U.S.C. § 2, the Commission went on to hold that Rambus had engaged in an unfair method of competition and unfair or deceptive acts or practices prohibited by § 5(a) of the Federal Trade Commission Act (“FTC Act”), id. § 45(a).

Rambus petitions for review. We grant the petition, holding that the Commission failed to sustain its allegation of monopolization. Its factual conclusion was that Rambus’s alleged deception enabled it either to acquire a monopoly through the standardization of its patented technologies rather than possible alternatives, or to avoid limits on its patent licensing fees that the SSO would have imposed as part of its normal process of standardizing patented technologies. But the latter — deceit merely enabling a monopolist to charge higher prices than it otherwise could have charged — would not in itself constitute monopolization. We also address whether there is substantial evidence that Rambus engaged in deceptive conduct at all, and express our serious concerns about the sufficiency of the evidence on two particular points.

During the early 1990s, the computer hardware industry faced a “memory bottleneck”: the development of faster memory lagged behind the development of faster central processing units, and this risked limiting future gains in overall computer performance. To address this problem, Michael Farmwald and Mark Horowitz began collaborating during the late 1980s and invented a higher-performance DRAM architecture. Together, they founded Rambus in March 1990 and filed Patent Application No. 07/510,898 (“the '898 application”) on April 18,1990.

As originally filed, the '898 application included a 62-page written description of Farmwald and Horowitz’s invention, 150 claims, and 15 technical drawings. Under the direction of the Patent Office, acting *460 pursuant to 35 U.S.C. § 121, Rambus effectively split the application into several (the original one and 10 “divisionals”). Thereafter, Rambus amended some of these applications and filed additional continuation and divisional applications.

While Rambus was developing a patent portfolio based on its founders’ inventions, the computer memory industry was at work standardizing DRAM technologies. The locus of those efforts was the Joint Electron Device Engineering Council (“JEDEC”) — then an “activity” of what is now called the Electronics Industries Alliance (“EIA”) and, since 2000, a trade association affiliated with EIA and known as the JEDEC Solid State Technology Association. Any company involved in the solid state products industry could join JEDEC by submitting an application and paying annual dues, and members could receive JEDEC mailings, participate in JEDEC committees, and vote on pending matters.

One JEDEC committee, JC 42.3, developed standards for computer memory products. Rambus attended its first JC 42.3 meeting as a guest in December 1991 and began formally participating when it joined JEDEC in February 1992. At the time, JC 42.3 was at work on what became JEDEC’s synchronous DRAM (“SDRAM”) standard. The committee voted to approve the completed standard in March 1993, and JEDEC’s governing body gave its final approval on May 24, 1993. The SDRAM standard includes two of the four technologies over which Ram-bus asserts patent rights — programmable CAS latency and programmable burst length.

Despite SDRAM’s standardization, its manufacture increased very slowly and asynchronous DRAM continued to dominate the computer memory market, so JC 42.3 began to consider a number of possible responses — among them specifications it could include in a next-generation SDRAM standard. As part of that process, JC 42.3 members received a survey ballot in October 1995 soliciting their opinions on features of an advanced SDRAM — which ultimately emerged as the double data rate (“DDR”) SDRAM standard. Among the features voted on were the other two technologies at issue here: on-chip phase lock and delay lock loops (“on-chip PLL/DLL”) and dual-edge clocking. The Committee tallied and discussed the survey results at its December 1995 meeting, which was Rambus’s last as a JEDEC member. Rambus formally withdrew from JEDEC by letter dated June 17, 1996, saying (among other things) that the terms on which it proposed to license its proprietary technology “may not be consistent with the terms set by standards bodies, including JEDEC.” Complaint Counsel’s Exhibit (“CX”) 887.

JC 42.3’s work continued after Rambus’s departure. In March 1998 the committee adopted the DDR SDRAM standard, and the JEDEC Board of Directors approved it in 1999. This standard retained SDRAM features including programmable CAS latency and programmable burst length, and it added on-chip PLL/DLL and dual-edge clocking; DDR SDRAM, therefore, included all four of the technologies at issue here.

Starting in 1999, Rambus informed major DRAM and chipset manufacturers that it held patent rights over technologies included in JEDEC’s SDRAM and DDR SDRAM standards, and that the continued manufacture, sale, or use of products compliant with those standards infringed its rights. It invited the manufacturers to resolve the alleged infringement through licensing negotiations.

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Bluebook (online)
522 F.3d 456, 380 U.S. App. D.C. 431, 86 U.S.P.Q. 2d (BNA) 1539, 2008 U.S. App. LEXIS 8662, Counsel Stack Legal Research, https://law.counselstack.com/opinion/rambus-inc-v-federal-trade-commission-cadc-2008.