PACT XPP Schweiz AG v. Intel Corporation

CourtDistrict Court, D. Delaware
DecidedJuly 26, 2024
Docket1:19-cv-01006
StatusUnknown

This text of PACT XPP Schweiz AG v. Intel Corporation (PACT XPP Schweiz AG v. Intel Corporation) is published on Counsel Stack Legal Research, covering District Court, D. Delaware primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
PACT XPP Schweiz AG v. Intel Corporation, (D. Del. 2024).

Opinion

IN THE UNITED STATES DISTRICT COURT FOR THE DISTRICT OF DELAWARE

PACT XPP SCHWEIZ AG,

,

Case No. 1:19-cv-01006-JDW v.

INTEL CORPORATION,

.

MEMORANDUM In law, one thing is paramount above all others: words matter. Lawyers and judges use different techniques to interpret the words depending on the context in which someone uses them. But they always matter. In this case, PACT XPP Schweiz AG made assertions to the U.S. Patent and Trademark Office to prevent the PTO from determining that its patent was obvious. The PTO accepted what PACT said and let the patent survive. Now, though, PACT wants to avoid the impact of what it told the PTO. It can’t do so. Having made specific assertions to the PTO about the scope of its invention, PACT is bound by the words it used. When I consider those words, I conclude that the remaining patent claims at issue in this case should be construed more narrowly than PACT suggests. And that narrow construction means that no reasonable juror could conclude that the accused devices that Intel Corp. makes infringe on PACT’s patent. I will therefore grant summary judgment on the remaining claims in this case. I. BACKGROUND A. Factual Background

PACT owns U.S. Patent No. 8,471,593 (“the ‘593 Patent”), which is directed to enabling efficient data processing by improving the data rate for transmissions within a logical cell array and bus system. In its most basic terms, the technology intends to

improve the internal architecture of microprocessor chips to increase processing speeds and expand memory storage. The Patent sets forth two independent claims and twenty- eight dependent claims. Independent claim 1 recites, in relevant part: a bus system flexibly interconnecting the plurality of processing cores, the plurality of memory units, and the at least one interface;

wherein:

the bus system includes a first structure dedicated for data transfer in a first direction and a second structure dedicated for data transfer in a second direction; and

each of at least some of the data processing cores includes a physically dedicated connection to at least one physically assigned one of the plurality of memory units, the assigned one of the plurality of memory units being accessible by another of the data processing cores via a secondary bus path of the bus system.

‘593 Patent, 12:31-44 (emphasis added to highlight disputed limitation). Independent claim 16 includes a substantially similar limitation. It recites, in relevant part: a bus system flexibly interconnecting the plurality of processing cores, the plurality of memory units, and the at least one interface;

wherein: the bus system includes a first structure dedicated for data transfer in a first direction and a second structure dedicated for data transfer in a second direction; and

each of at least some of the data processing cores includes a dedicated connection to at least one assigned one of the plurality of memory units each situated such that no other data processing core and no other memory unit is positioned between the respective data processing core and the respective assigned memory unit, the assigned one of the plurality of memory units being accessible by another of the data processing cores via a secondary bus path of the bus system.

at 13:38-55 (emphasis added to highlight disputed limitation). Intel manufactures a range of microprocessors that are “capable of executing instructions, performing computations on data, and reading from and writing to memory.” (ECF No. 591 at 4.) This includes the Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Coffee Lake, Ice Lake, Kaby Lake, Amber Lake, Whiskey Lake, Cascade Lake, Cannon Lake, and Lakefield Processors, all of which PACT alleges infringe certain claims of the ‘593 Patent. B. Procedural History On May 30, 2019, PACT filed a complaint asserting that Intel infringed 423 claims from twelve of its patents, including the ‘593 Patent. The scope of the dispute has narrowed significantly since. Through review, reexamination, summary judgment, and PACT’s voluntary dismissal of some claims with prejudice, only claims 1, 2, 4, 5, 10, 11, 14, 15, 16, 17, 21, and 22 of the ‘593 Patent remain in issue. During the claim construction proceedings in this case, I did not construe the term “dedicated connection” because the Parties did not request it. Intel raised the possibility of a need for construction after the hearing, but I denied that request while leaving open

the possibility of alternative construction in a future motion. On June 21, 2022, the Parties filed cross-motions for summary judgment. In an Order dated March 24, 2023, I granted in part and denied in part both. I denied Intel’s

Motion as it pertained to the ‘593 Patent because a genuine dispute of material fact existed as to whether Intel’s accused devices practiced two of the patent’s limitations: namely, “(1) a system with two dedicated connections transferring data in different directions, and (2) processors with exclusive connections to corresponding memory units.”

(D.I. 399 at 8.) On June 10, 2021, Intel requested EPR of the ‘593 Patent. It argued that prior art, including U.S. Patent No. 6,457,087 to Fu, rendered the ‘593 Patent’s claims obvious. The USPTO instituted re-examination on August 13, 2021, and issued non-final rejections on

October 4, 2022, and March 30, 2023. In the first rejection, the Examiner rejected the claims at issue for the ‘593 Patent as obvious because Fu recites a structure wherein devices, such as processors, connect to memories via a chain including a flow control unit

(FCU), memory control unit (MCU), memory path, memory bus, and node switch. Because this internal transit grid creates a pathway between all memories and processors within the structure, and because the switches could be configured to allow for a processor to access the MCU to the exclusion of other devices, this structure constitutes the “dedicated connection” that the ‘593 Patent contemplates. In reaching that conclusion, the Examiner rejected PACT’s argument that if multiple processors can connect to the memory line,

then there is no dedicated connection. Instead, the Examiner concluded that “all that is required . . . is that there be a physically dedicated connection, i.e. a direct, uninterrupted connection, between a core and a memory unit.” (D.I. 598-9 at 27.)

In response, PACT argued that Fu fails to disclose a “dedicated connection” because it recites a structure in which “the memories to which one of the processors is connectable via the FCU is also available to connection by another of the processors over a same line of the FCU.” (D.I. 598-10 at 10 (numbered identifiers omitted).) Under PACT’s

reading, the Examiner’s interpretation of “dedicated” as synonymous with “direct” and “uninterrupted” was overbroad. Instead, citing lay dictionary definitions and the claim language, PACT insisted that a person of ordinary skill in the art would understand that a direct connection is a dedicated connection when that connection is devoted to

connecting two units while excluding connection to any and all other units. Therefore, “a communication line(s) that is by a multitude of different devices cannot be a ‘dedicated’ connection.” ( at 11 (emphasis in original).) As PACT argued, it is not enough

for a processor to connect to the memory via an uninterrupted, direct route. To fall within the ‘593 Patent’s “dedicated connection” limitation, that connection must connect one processor to one memory. Upon consideration of PACT’s proposed constructions for “dedicated” as “devoted to a particular purpose or designed to interconnect exclusively,” the Examiner adopted

the latter as the term’s plain and ordinary meaning. (D.I.

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PACT XPP Schweiz AG v. Intel Corporation, Counsel Stack Legal Research, https://law.counselstack.com/opinion/pact-xpp-schweiz-ag-v-intel-corporation-ded-2024.