MEMORANDUM OPINION
ELLIS, District Judge.
Twenty patents covering different semiconductor circuitry devices and fabrication
processes are at issue in these consolidated patent infringement actions, twelve of which are asserted by NEC Corporation and eight of which are asserted by Hyundai Electronics Industries Co.
One of these patents, NEC’s U.S. Patent No. 4,054,865 (the ’865 patent), entitled “Sense Latch Circuit For a Bisectional Memory Array,” is now before the Court on the parties’ cross motions for summary judgment on the issue of infringement and on Hyundai’s motion for summary judgment on the issue of validity. Disposition of these motions requires claim construction under
Markman v. Westview Instruments, Inc.,
517 U.S. 370, 116 S.Ct. 1384, 134 L.Ed.2d 577 (1996), which, in turn, leads to the conclusion that Hyundai’s products do not literally infringe the ’865 patent, but that remaining disputed factual issues preclude summary judgment on the issues of validity and infringement under the doctrine of equivalents.
I. The ’865 Patent
The ’865 patent involves the circuitry connecting the sense amplifiers within a memory cell array and the input/output line, which carries information in and out of the memory cells. In particular, the ’865 patent relates to the manner in which an individual memory cell in a two-dimensional memory cell array is accessed, either in a “read” operation, where the value of the data stored in the memory cell is determined, or in a “write” operation, where the value of the individual data bit is stored in the cell. Claim 1 of the ’865 patent concerns the DRAM “read” function and claims 6 through 8 concern the DRAM “write” function.
A dynamic random access memory device (DRAM) is a basic type of memory chip that stores logic information in the form of binary digits, or “bits.” A bit may have a value of either “1” (signifying a high charge) or “0” (signifying a low charge). Each individual memory cell within a DRAM stores an electrical charge that determines the value of one data bit of information. The cells are connected to the circuitry outside the memory array through a grid of electrical lines known as “bit lines” and “word lines” with each word line identified by a unique “row address” and each bit line identified by a unique “column address.” An individual memory cell can be accessed by presenting the DRAM with the unique column address and row address combination corresponding to the cell’s location. Information in the form of electrical charge passes into and out of a selected memory cell through its corresponding bit line.
To read a particular memory cell, a signal is applied to the particular word line that is connected to that memory cell. In this fashion, power is applied to every memory cell in the row containing the selected cell because all cells in the row are attached to the same word line. To isolate the selected memory cell from all the other cells in the row along the activated word line, only the particular bit line and sense amplifier associated with the selected memory cell are “sensed” to determine the state of the cell. Column decoders control gates that select the particular bit line connected to a selected memory cell. Thus, a particular' memory cell is accessed by providing an activation signal through the word line connected to a row of memory cells containing the selected cell, and sensing the bit lines connected to the column that includes the selected memory cell. In a write operation, the same basic operation occurs, but in this event, a write gate is activated, allowing information to flow through the input/output line and into the memory cells.
The prior art as identified in the ’865 patent uses an “unbalanced” sensing scheme. The individual sense amplifiers are connected to the input/output line for the memory array through a column decoder and a gate located on only one side of the sense amplifier, through bit lines lying on only one side of the amplifier. For memory cells lying both above and below the sense amplifier, the output passes through this gate and column decoder to the output amplifier. There, the output
amplifier compares the signal coming from one side of the sense amplifier with a reference voltage to determine the value of that signal. Similarly, in “write” operations, a single write gate lying on one side of the sense amplifiers is used to apply a signal to reach cells on both sides of the sense amplifier. Thus, in the prior art, represented in Figure 1 of the ’865 patent,
the array of memory cells is divided into two halves by a series of sense amplifiers, but the individual memory cells in both halves are accessed from only one side during both read and write operations. In this prior art, output amplifiers, which amplify the signals created by the relatively small sense amplifiers, function by comparing the output signal on one side of the sense amplifier with a reference voltage and then sending a logical “1” or “0” to the output terminal depending on the relative voltage level of the signal.
In contrast to this “unbalanced” sensing scheme, the ’865 patent relies on the concept of “balanced” sensing. As illustrated by Figure 4 of the ’865 patent,
column decoders and gates are located on both sides of the sense amplifiers, one at the top of the memory cell array and one at the bottom of this array. Thus, each of the two bit lines in a bit line pair has its own input/output line, and each input/output line is operatively connected with the output amplifier during a read operation. In a read operation, signals from both bit lines of a bit line pair are transferred to an output amplifier when a word line is activated. The signals from both bit lines (which will be complementary to one another, based on the operation of the sense amplifier) will be transferred through their respective gates on each side of the memory cell array activated by their respective column decoders to the output sense amplifier. The arrangement shown as the invention in the ’865 patent is called ‘balanced’ because both sides of the sense amplifier output are used equally. Thus, instead of comparing the output of one side to a reference voltage, the output amplifier compares the two complementary signals from both sides of the sense amplifier, resulting in a-faster, more reliable read operation.
Similarly, in a “write” operation, a pair of write gates are used, which apply complementary signals through a pair of gates activated by a patr of column decoders to write a bit of data in the selected memory cell. Once again, the operation is “balanced” in that signals are applied from both sides of the sense amplifier.
A specific problem with early dynamic sense amplifiers was their inability to perform a “read modify write” (RMW) operation. In an RMW cycle, the memory cell is first read; then new information from outside the chip is written into the memory location that has just been read. While this cycle is quite efficient in terms of system operation, it requires that the new information overwrite the potentially opposite state of the sense amplifier. Claims 6, 7, and 8 of the patent address the RMW problem by sending complementary input signals simultaneously to both sides of the sense amplifiers through the same data lines used for the read operations. The direct driving of both bit lines in a bit line pair by complementary signals is sufficient to change the existing condition of the sense amplifier (la, the condition that exists after reading a memory cell) and thus permits a write operation to be performed in the middle of a read cycle without any delay. Claims 1 and claims 6 through 8 of the patent are specific to the “balanced sensing” concept.
II. Claim Construction
Infringement analysis involves a two-step determination: first, the proper construction of the asserted claim and then a determination whether the claim, as properly construed, reads on the accused product or method. Claim construction is a question of law.
Markman v. Westview Instruments, Inc.,
52 F.3d 967, 976 (Fed.Cir.1995) (en banc),
aff'd,
517 U.S. 370, 116 S.Ct. 1384, 134 L.Ed.2d 577 (1996). A product infringes a claim in a patent if every element of the invention, as set out in the claim, can be found in the product literally or by substan
tial equivalent. Thus, as a prerequisite to any infringement determination, it is necessary to construe the elements of claim 1 and claims 6 through 8.
When construing a claim, a court principally consults the evidence intrinsic to the patent: namely, the claims themselves, the written description portion of the specification, and the prosecution history of the patent.
See Vitronics Corp. v. Conceptronic, Inc.,
90 F.3d 1576, 1582-83 (Fed.Cir.1996). Extrinsic evidence, which consists of material outside the patent and its file history and includes expert testimony, dictionaries, learned treatises, and the like, may be considered only “for the court’s understanding of the patent, not for the purpose of varying or contradicting the terms of the claims.”
Markman,
52 F.3d at 981.
Because the claims define the invention,
the analysis of the intrinsic evidence focuses first on the words of the claims themselves, giving the claim terms their “ordinary and customary meaning.”
Vitronics,
90 F.3d at 1582. A term should not be interpreted contrary to its customary meaning unless the specification clearly explains this special definition.
Id; Markman,
52 F.3d at 979 (“For claim construction purposes, the description may act as a sort of dictionary, which explains the invention and may define terms used in the claims.”). Nevertheless, a paten-tee may choose to be his or her own lexicographer and use terms in a manner other than their ordinary meaning provided that the patent specification or file history clearly discloses any such special or alternative meaning.
Vitronics,
90 F.3d at 1582.
Beachcombers v. WildeWood Creative Prods., Inc.,
31 F.3d 1154, 1158 (Fed.Cir.1994).
In the event the claim language alone is not dispositive, analysis should focus next on the specification of the patent, which is highly relevant to the claim interpretation process and is, in fact, “the single best guide to the meaning of a disputed [claim].”
Vitronics,
90 F.3d at 1582.
See also Gentry Gallery, Inc. v. Berkline Corp.,
134 F.3d 1473, 1478-80 (Fed.Cir.1998). It follows that a proposed claim interpretation that excludes the preferred embodiment would rarely, if ever, be correct.
Vitronics,
90 F.3d at 1583. In those instances where an element of a claim in issue is expressed as a means for performing a specific function, the element must be construed to cover the corresponding structure described in the specification or its equivalents.
See
35 U.S.C. § 122, ¶ 6;
see also Sofamor Danek Group, Inc. v. DePuy-Motech, Inc.,
74 F.3d 1216, 1220 (Fed.Cir.1996).
The patent’s prosecution history or “file wrapper” may also aid in proper claim construction. Statements made in the course of a patent’s prosecution may shine a bright light on the scope and meaning of the claims. Thus, courts have “broad power to look as a matter of law to the prosecution history of the patent in order to ascertain the true meaning of language used in the patent claims,” since this history may demonstrate the patentee’s understanding of the relevant terms at the time of application.
Markman,
52 F.3d at 980;
see also Vitronics,
90 F.3d at 1582-83.
In those relatively unusual instances where the intrinsic evidence
(i.e.,
the claims, the specification, and the prosecution history) is not sufficient to resolve ambiguity in claim language, courts may resort to extrinsic evidence, including expert testimony, to resolve the dispute.
Vitronics,
90 F.3d at 1583;
Hormone Research Found., Inc. v. Genentech, Inc.,
904 F.2d 1558, 1562 (Fed.Cir.1990).
These principles of claim construction must be brought to bear on the disputed elements of claims 1 and 6 through 8 the ’865 patent, considered separately below.
A. First and second row groups
Claims 1, 6, 7, and 8 of the ’865 patent describe the relevant memory cell array as “being divided into first and second row groups.” NEC argues that this language does not require any physical division
between the first and second row groups and that, as a result, Hyundai’s DRAM devices, in which the “groups” are physically intermingled, infringe the ’865 patent. Put another way, NEC contends that the terms of the ’865 patent include “folded bit line” architecture, while Hyundai argues that the “first and second row groups” language narrows the patent so that it necessarily requires “open bit line” architecture. The issue is significant as the accused Hyundai product employs folded bit line architecture.
Open bit line architecture and folded bit line architecture refer to two different methods of arranging bit lines in a memory cell array. In such an array, pairs of bit lines extend from circuits commonly called sense amplifers (but called “differential amplifiers” in the ’865 patent) to connect a column of memory cells. The differential sense amplifier is the circuit that must detect and amplify small electrical signals in a DRAM chip. In early DRAM chips, differential sense amplifiers were placed in the center of an array of memory cells, with one bit line extending up and one bit line extending "down from each differential sense amplifier to connect a column of memory cells. This architecture is called “open bit line.”
As discussed above, word lines run across and perpendicular to bit lines and control access to all the memory cells in a particular row. In open bit architecture, any given word line crosses only one of the two bit lines entering ■ a differential sense amplifier. When the word line is activated to access the row of memory cells, it creates electrical “noise” in every bit line it crosses. The noise can cause the differential sense amplifier to supply erroneous information. To reduce or eliminate this problem, folded bit lines were introduced in the 1970s.
With folded bit lines, the row of differential sense amplifiers is placed on one side of an array of memory cells, and both bit lines extend from the same side of each differential amplifier to the corresponding column of memory cells. This way, every word line crosses both bit lines entering a differential sense amplifier, and equal amounts of electrical noise are introduced to each bit line. Because the differential sense amplifier responds to the difference in voltage between the two bit lines, adding the same electrical noise to each one has no effect.
In open bit line architecture, then, word lines (and thus row columns lying along word lines) are physically divided into two groups: those lying above and those lying below the differential sense amplifier. In folded bit line architecture, the differential sense amplifiers do not so divide the word lines, though the word lines are functionally and electrically identical in folded bit line and open bit line architecture. NEC contends that the reference in claim 1 of the ’865 patent to first and second row groups merely refers to two sets of word lines identified by distinct functions. In other words, according to NEC, a “group” of word lines (as that word is used in the ’865 patent) refers to any set of word lines that shares a common characteristic. While in open bit line architecture, one group of word lines connects to those memory cells above the differential sense amplifiers and one group connects to those below the differential sense amplifiers, in folded bit line architecture one “group” of word lines controls memory cells connected to the right side of each differential sense amplifier and one “group” of word lines controls memory cells connected to the left side of each differential sense amplifier. NEC argues that the fact that the row groups are physically intermixed in folded bit line 'architecture does nothing to mask their separate identities.
The starting point in the analysis is the language of the claim, which makes clear that it is the memory array itself — in other words, the two-dimensional arrangement of memory
cells — ’that is divided into first and second row groups. If the division of the array into row groups is understood as a physical division, in which one set of row groups arranged along word lines is physically separate and distinct from the second set of row groups arranged along word lines, the claims must necessarily cover only open bit line architecture.
Figures 1 of the ’865 patent discloses the “prior art” as understood by the ’865 inventor, while Figure 4 represents the invention. NEC concedes that both figures depict open bit line architecture. Nor is this depiction of the invention surprising, since claim 1 of the ’865 patent appears to contemplate open bit line architecture. First, claim 1 requires “a plurality of memory cells arranged in an array of rows and columns,” and goes on to require that the “said memory cell array [be] divided into first and second row groups.” Thus, the claim requires the division of the physical, two-dimensional arrangement of cells that is the array into two parts; such language strongly suggests physical division. The language of claim 1 in combination with the illustrations of the invention in Figures 4-6 of the ’865 patent indicate that the inventor intended to include only open bit line structures or architecture within the terms of the patent.
Moreover, claim 1 of the '865 patent requires that each differential sense amplifier have a first input terminal connected to memory cells in the first row group in one column, and a second input terminal connected to memory cells in the second row group in the “same column as that connected to said first terminal.” Looking at Figure 4 of the ’865 patent, for example, this requires that the leftmost sense amplifier (12) be connected to the leftmost column of memory cells (10, 10'), which runs from the top to bottom of the page through input terminals (1, 2) connected to the leftmost bit lines (16, 16'). Again, the language of the claims and the patent figures suggest that the half bit lines must be connected to half bit lines extending to memory cells in separate row groups in the same column. Such construction is inconsistent with folded bit line architecture. Thus, the “said memory array being divided into first and second row groups” element in claims 1, 6, 7, and 8 is correctly understood as referring to two physically separated rows of word lines and hence includes only open bit line structures or architecture.
A different conclusion in this regard would entail the somewhat surprising result that the scope of the ’865 patent would include a feature not yet publicly known at the time of the ’865’s filing. According to the parties, folded bit line architecture was first disclosed in U.S. Patent No. 4,025,907, filed on July 10, 1975, months after the April 30, 1975, filing date for the ’865 patent.
Given this construction, Hyundai’s accused devices do not literally infringe the ’865 patent as they employ folded bit line architecture. Whether the devices infringe under the doctrine of equivalents is a question of fact that remains open for trial.
B. Operatively connecting
Claim 1 of the ’865 patent includes the following limitations:
first means for operatively connecting the first terminal of a selected one of said differential amplifiers to the first terminal of said sense amplifier, and second means for operatively connecting the second terminal of a selected one of said differential amplifiers to the second terminal of said sense amplifier.
Claims 6, 7, and 8 of the ’865 patent include limitations using similar language, as follows: first means for operatively connecting the first terminal of the selected differential amplifier to said first input-output bus line, and
second means for operatively connecting the second terminal of said selected differential amplifier to said second input-output bus line.
These disputed claim elements are expressed in “means plus function” language, which, as noted, must be construed to cover the corresponding structure described in the specification or its equivalents.
See
35 U.S.C. § 122, ¶ 6;
see also Sofamor Danek Group,
74 F.3d at 1220. The parties agree that the structures constituting the first and second means are the two switching gate transistors pic
tured as Q4 and Q4 in Figure 5 of the ’865 patent and that these two transistors must “operatively eonnect[ ]” the differential sense amplifier terminals with the output sense amplifier terminals and the inpui/output data bus lines. What is sharply disputed is the scope of the phrase “operatively connecting.” NEC argues that this phrase requires a direct electrical connection between the differential sense amplifier and what is usually referred to as an output amplifier, but which is called a sense amplifier in the ’865 patent. Hyundai counters that this phrase must be construed more broadly to include information transferred through a type of buffer circuit, called a “source follower,” in which the output of the differential sense amplifier is used to operate a gate which, in turn, controls another signal generated from the power supply that controls the output sense amplifier, but which does not create any electrical connection between the two amplifiers.
The switching gate transistors Q4 and Q4’ pictured in Figure 5 of the ’865 patent are configured so as to create a direct source-drain electrical connection between the two amplifiers when they are in their active state.
Indeed, such a configuration would appear to be necessary to achieve the benefit of the patent: namely, comparing the actual outputs of the two sides of the differential sense amplifier in order to determine logic. level, rather than merely comparing the signal on one side with a reference voltage on the other. Under Hyundai’s construction, the first and second means elements of Claim 1 include a configuration in which there is no direct current path between the outputs of the differential sense amplifier to compare at the output sense amplifier. Such a construction is unpersuasive as it would frustrate the patent’s purpose. Nor is there any doubt that the patent’s purpose is a proper interpretive guide; the Federal Circuit has held that the purpose of the invention may guide claim construction since “the problem the inventor was attempting to solve, as discerned from the specification and prosecution history, is a relevant consideration” in construing claims.
CVI/Beta Ventures, Inc. v. Tura LP,
112 F.3d 1146, 1160 (Fed.Cir.1997);
see also Applied Materials, Inc. v. Advanced Semiconductor Materials Am., Inc.,
98 F.3d 1563, 1573 (Fed.Cir.1996).
Construing the phrase “operatively connected” to require such an electrical connection is also supported by the file history of the ’865 patent, in which the patent applicant distinguished the Lindell patent (U.S. Patent No. 3,838,295) from the ’865 patent based upon the former’s lack of electrical connection between the differential sense amplifier and the output sense amplifier. While the original ’865 patent application used the term “electrically connecting” and later amended this term to “operatively connecting,” there is no basis for concluding that this amendment was intended to change the scope of the patent, as the rationale given for the modification of the language was simply a desire to describe the invention “in proper idiomatic English.” As a result, the phrase “operatively connecting” in Claims 1, 6, 7, and 8 of the patent must be construed to require a direct source-drain electrical connection, for only then would the object of the invention be accomplished, namely, “to provide a memory circuit capable of operation without the need for applying a reference voltage to one input of the output sense amplifier.”
C. Simultaneously supplying
The parties dispute the meaning of the term “simultaneously” in the “means for simultaneously supplying the first input-output bus line with one of a logic 1 or 0 signal and the second input-output bus line with the other of a logic 1 or 0 when the memory circuit is enabled in the write operation mode” element of claims 6, 7, and 8 of the ’865 patent. Hyundai argues that two events happen “simultaneously” when one continues while the other occurs, claiming that this is the meaning of the term “simultaneously” in ordinary English usage, and that the term “simultaneously” in the ’865 patent should be construed accordingly. Specifically, Hyundai argues that the application of a logic “1” signal to one data bus line while the other data bus line is already at a logic “0” signal works to supply a “1” and “0” signal to the two input/output lines “simultaneously.” NEC advocates a narrower construction of
“simultaneously,” reading it to require both events (i.e., the application of a “1” and a “0” signal) to commence at the same time.
Words in a claim are usually “given their ordinary and customary meaning,” but a pat-entee “may choose to be his own lexicographer and use terms in a manner other than their ordinary meaning, as long as the special definition of the term is clearly stated in the patent specification or history.”
Vitronics,
90 F.3d at 1582. The technological context of the claim may also make reliance on a common, dictionary definition for a word inappropriate, since “[a] word describing patented technology takes its definition from the context in which it was used by the inventor.”
Anderson v. International Eng’g and Mfg., Inc.,
No. 98-1062, 1998 WL 770652, at *3 (Fed.Cir. Nov.2, 1998).
The context of the word “simultaneously” in the ’865 patent compels construction of the term “simultaneously” according to the narrower definition propounded by NEC. In the ’865 patent, the structure of the “means for simultaneously supplying” is a pair of write gates shown as 19 and 19' ánd transistors Q26 and Q26 in Figures 4 and 5 of the patent. The parties do not dispute that these devices are activated by the same signal at the same time. The specification states that “the low and high level signal [sic] are applied to terminals IN and /IN through the write timing signal W, respectively.” The fact that these high and low signals are applied by the same signal at the same time is made even more explicit by the prosecution history of the ’865 patent, which includes the statement that “[i]f it is assumed that the potential at the terminal of the differential amplifier is at the logic “0” level after a read operation, and the potential at the other is at the logic “1” level, to write logic “1” level information in the memory cells, the logic “1” and “0” level signals are applied to the terminals /IN and IN
at the same time
through the write gates operated by the write timing signal W” (emphasis added). Thus, in a “read modify write” operation complementary signals are sent at the same time to the terminals at both sides of the differential sense amplifier, rather than conveyed through a two-step process involving a greater time lag, in which both terminals are brought to the same level initially and then one of the terminals is brought to the desired level. Since this ability to send complementary signals quickly during a RMW operation appears to lie at the heart of the ’865 patent, “simultaneously” is construed as meaning starting and subsisting at the same time.
Given these conclusions' concerning the scope of the disputed claims of the ’865 patent, questions of validity and infringement under the doctrine of equivalents must be deferred until trial as issues' of disputed fact remain. Furthermore and equally importantly, postponement of these issues until trial permits the independent expert appointed pursuant to Rule 706, Fed.R.Evid., to tender his opinions on the infringement and validity of the ’865 patent. Given the obscurity of the technology in dispute, expert witnesses play a crucial role in communicating the facts and theories in this case. Throughout the pretrial phases of these actions, the parties’ experts have skillfully elucidated the relevant technology, yet it has also grown clear that the parties’ experts have, unfortunately, but understandably, become technical advocates for their respective causes, vehemently disagreeing in every particular and abandoning that independence which makes the testimony of such witnesses most helpful. To remedy this situation, several Rule 706 experts have been appointed to testify at trial in these actions, and the imminent availability of these independent, informed opinions counsels hesitation in disposing of these matters during pretrial absent the benefit of their testimony.
An appropriate order will enter.
The Clerk is directed to send copies of this Memorandum Opinion to all counsel of record.
APPENDIX 1
[[Image here]]
APPENDIX 2
APPENDIX 3
APPENDIX 4
APPENDIX 5
ORDER
These five patent infringement actions are between the samé antagonists and involve twenty (20) patents covering different semiconductor circuitry devices. The number, diversity, complexity, and subtlety of the patents at issue render it unreasonable to demand that any single jury or juror hear and determine all the facts contested by the part
ies.
Indeed, unless the jury is staffed with electrical engineers or others versed in transistor circuitry, it is unlikely that it could successfully engage and understand the technical issues presented in a reasonable amount of time.
Given the obscurity of the technology in dispute, the parties’ expert witnesses play a crucial role in communicating the facts and theories of the ease. Through the pretrial phases of these actions, the experts have skillfully and helpfully elucidated the relevant technology. Nevertheless, the pretrial phases of these actions have also revealed that the parties’ experts have, unfortunately, but understandably, become technical advocates for their respective causes, vehemently disagreeing in every particular and abandoning that independence which makes the testimony of such witnesses most helpful to finders of fact and law.
Both the inappropriateness of calling a jury to hear these matters and the clearly adversarial stance of the expert witnesses present problems to be addressed through tailoring a fair and reasonable trial procedure suitable for these cases. Accordingly, the Court hereby ORDERS that trial of these actions be conducted according to the following procedures:
(1)All of the above matters shall be consolidated for the purposes of trial, although trial will proceed with the Court considering one patent at a time and issuing findings of fact and conclusions of law upon the conclusion of the presentation of evidence on each patent, rather than upon the conclusion of the evidence on all the patents. The liability and damages portions of trial shall be bifurcated and tried separately. More precisely, the trial of these consolidated cases shall proceed with the Court hearing all validity and infringement issues for each patent, one at a time, and rendering findings of fact and conclusions of law either in writing or orally from the bench immediately following the presentation of evidence pertaining to such patent. Issues of liability and damages shall be bifurcated with the damages phase of the trial with regard to those patents found valid and infringed to occur immediately upon the conclusion of the liability phase.
(2) All matters and issues in the consolidated cases shall be tried to the Court without a jury, the parties having waived a jury in all the cases.
(3) An expert witness or expert witnesses will be appointed by the Court pursuant to Rule 706, Fed.R.Evid. The criteria for appointment of a Rule 706 expert or experts shall be expertise and experience in the relevant technology, complete impartiality, and the absence of any conflict of interests.
(4) The process for identifying and selecting Rule 706 experts shall be as follows:
(a) The parties’ counsel are directed to meet and confer to develop a list of candidates for various areas of the relevant technology.
(b) The parties’ counsel shall jointly contact these listed candidates.
(c) During these initial joint contacts, parties’ counsel shall ascertain the following:
(i) whether each candidate has ever been employed by or affiliated with NEC or Hyundai or their affiliates;
(ii) whether any close friends or relations of the candidate have been employed by or affiliated with NEC or Hyundai or their affiliates;
(iii) whether each candidate has ever previously testified as an expert witness and if so, on what occasion and on what subject;
(iv) the relevant education and experience of each candidate;
(v) whether each candidate is an owner or inventor of any patent and, if so, the subject matter of each such patent, briefly described;
(vi) whether each candidate is familiar with any of the patents in suit;
(vii) whether each candidate is willing ■ to serve as a court-appointed expert witness in the consolidated cases.
(d) During these initial joint contacts, parties’ counsel shall inform each candidate of the following:
(i) the nature of the work required;
(ii) the method and form of payment;
(iii) the fact that this task may demand a substantial amount of time, depending on the number
of
expert witnesses ultimately appointed.
(e) During these initial joint contacts, parties’ counsel shall make clear that the purpose of this initial contact is limited to inquiries regarding the candidate’s qualifications, availability, and willingness to serve as a court-appointed expert. Parties’ counsel shall ask no questions of any candidate concerning the matters at issue in these cases.
(f) Based upon these joint inquiries, counsel for the parties shall jointly submit to the Court by 5:00 p.m., Wednesday, October 28, 1998, a list of candidates for appointment as Rule 706 experts. The list shall note any candidate whom the parties agree is most suitable for appointment. The agreement of parties as to the desirability of a particular candidate or candidates will be accorded significant weight by the Court in its selection of the Rule 706 expert or experts.
(g) Based on this list, the Court will initiate further contact with candidates as necessary and make its selection of the Rule 706 expert or experts based on the criteria set forth in paragraph (3) above.
(5)The Rule 706 expert or experts will be compensated as follows:
(a) The reasonable fees and expenses of any such appointed experts shall be paid and shared equally by the parties.
(b) Each appointed expert shall send an itemized monthly statement to the parties, setting forth the hours worked, a description of the work or tasks performed during these hours, the expert’s hourly rates, and a description of the nature and amount of any expenses.
(c) NEC and Hyundai shall each pay one-half of any expert’s statement within thirty (30) days of receiving it.
(d) Should either party have any objections to a statement, they must promptly file the objection with the Court, not the expert, and the Court will then resolve the matter, without disclosing to the expert which party has objected.
(6) The role of the Rule 706 expert or experts will be to assist the parties’ experts in elucidating the relevant technology and to offer independent, technical opinions as to disputed factual matters.
(7) The Court will not communicate with any Rule 706 expert on any subject touching the merits of these cases other than in open court or with the knowledge and consent of the parties. And neither party, including counsel, shall communicate with any such expert on any subject other than in open court or with the Court’s prior consent. •
(8) Prior to trial, the parties shall jointly submit to the Rule 706 expert or experts a packet of information for each of the patents at issue relevant to that expert’s testimony. Each packet should include:
(a) a copy of the patent;
(b) the opinions of the parties’ experts regarding the issues raised by that patent;
(c) a copy of each Court order setting forth any claim interpretation rulings;
(d) a list of the specific questions or issues to be addressed by the Rule 706 expert or experts;
(e) copies of the written direct testimony of each party expert.
(9) At trial, expert testimony shall be presented and proceed as follows:
(a) Each party shall submit the testimony of its expert witness in advance, in written question and answer form. For good cause, the Court in certain instances may permit the parties to elicit further direct oral testimony from their own experts, but the written document will be the
primary, if not sole, vehicle through which the parties’ expert direct testimony is presented. The parties shall submit to the Court the written direct testimony of their experts on all patents in issue at or before 5:00 p.m., Friday, November 20,1998.
(b) The parties’ experts shall then be subject to cross-examination by opposing counsel and to further questions from the Court.
(c) The 706 expert or experts will be invited to submit questions for cross-examination of the parties’ experts to the Court, and if the Court approves these submissions, it will present these question to the parties’ experts during cross-examination.
(d) Use of demonstrative exhibits explicative of direct testimony is not foreclosed, to the degree these are helpful or necessary.
(10) The Rule 706 expert or experts will be asked to offer opinions on the relevant issues addressed by the parties’ experts. Each party will have ample opportunity to cross-examine the 706 expert or experts.
(11) To the extent possible, the parties shall stipulate to any facts that would require the calling of any other witnesses. In this regard, parties are directed to meet and confer as to stipulations of fact to whatever extent is necessary to reach as broad an agreement as possible. Parties are instructed to submit their joint stipulations of fact to the Court at or before 5 p.m., Friday, November 20,1998.
(12) The parties are each directed to submit proposed findings of fact and conclusions of law to the Court at or before 5 p.m., Monday, November 30, 1998. Trial will commence on Wednesday, December 2, 1998.
The Clerk is directed to send copies of this Order to all counsel of record.