Lsi Corporation v. Regents of the University of Minnesota

CourtCourt of Appeals for the Federal Circuit
DecidedAugust 11, 2022
Docket21-2057
StatusPublished

This text of Lsi Corporation v. Regents of the University of Minnesota (Lsi Corporation v. Regents of the University of Minnesota) is published on Counsel Stack Legal Research, covering Court of Appeals for the Federal Circuit primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Lsi Corporation v. Regents of the University of Minnesota, (Fed. Cir. 2022).

Opinion

Case: 21-2057 Document: 40 Page: 1 Filed: 08/11/2022

United States Court of Appeals for the Federal Circuit ______________________

LSI CORPORATION, AVAGO TECHNOLOGIES U.S. INC., Appellants

v.

REGENTS OF THE UNIVERSITY OF MINNESOTA, Appellee ______________________

2021-2057 ______________________

Appeal from the United States Patent and Trademark Office, Patent Trial and Appeal Board in No. IPR2017- 01068. ______________________

Decided: August 11, 2022 ______________________

KRISTOPHER L. REED, Kilpatrick Townsend & Stockton LLP, Dallas, TX, argued for appellants. Also argued by EDWARD JOHN MAYLE, Denver, CO.

PATRICK JOSEPH MCELHINNY, K&L Gates LLP, Pitts- burgh, PA, argued for appellee. Also represented by MARK G. KNEDEISEN, ANNA SHABALOV, CHRISTOPHER MICHAEL VERDINI; THEODORE J. ANGELIS, Seattle, WA. ______________________

Before DYK, REYNA, and HUGHES, Circuit Judges. Case: 21-2057 Document: 40 Page: 2 Filed: 08/11/2022

DYK, Circuit Judge. The Regents of the University of Minnesota (“UMN”) sued LSI Corporation and Avago Technologies U.S. Inc. (collectively, “LSI”) for infringement of U.S. Patent No. 5,859,601 (“’601 patent”) in the District of Minnesota. LSI petitioned the Patent Trial and Appeal Board (“Board”) for inter partes review of the ’601 patent, and the Board insti- tuted review on claims 13, 14, and 17 on anticipation theo- ries based on two prior-art references, U.S. Patent Nos. 5,392,270 (“Okada”) and 5,731,768 (“Tsang”). The Board concluded that claim 13 was unpatentable in view of Okada and that claims 14 and 17 were not shown to be unpatent- able in view of either reference. In finding that LSI failed to show unpatentability of claims 14 and 17, the Board held that LSI failed to timely raise its theory that Tables 8 and 9 of Okada anticipate claims 14 and 17 and that, in any event, Tables 8 and 9 did not anticipate. As to Tsang, the Board held that the reference was not prior art because it was not “by another” under 35 U.S.C. § 102(e). 1 LSI ap- peals the Board’s decision as to claims 14 and 17. We af- firm. BACKGROUND I The ’601 patent addresses error rates related to record- ing data to computer storage devices. Some input data se- quences contain “error-prone binary data patterns.” ’601 patent, col. 2, ll. 40–46. Dr. Jaekyun Moon, a UMN profes- sor at the time, and Dr. Barrett J. Brickner, a UMN grad- uate student at the time, developed maximum transition- run (“MTR”) coding to reduce these error-prone patterns, and their work became the basis for the ’601 patent. Id. MTR coding as described in the ’601 patent involves

1 Because the ’601 patent was filed before the Amer- ica Invents Act (“AIA”), we use the pre-AIA statute. Case: 21-2057 Document: 40 Page: 3 Filed: 08/11/2022

LSI CORPORATION v. 3 REGENTS OF THE UNIVERSITY OF MINNESOTA

receiving sequences of input data blocks with error-prone patterns and converting (i.e., encoding) each input data block into a corresponding “codeword” that avoids the er- ror-prone patterns. Id. at col. 4, l. 46–col. 5, l. 20. Dr. Moon and Dr. Brickner understood that the number of consecu- tive bit transitions in the input data sequence, i.e., binary bit transitions from 0 to 1 or 1 to 0, was an important source of error. Thus, MTR coding as described in the ’601 patent converts input data blocks into codewords that (1) “impose[] a limit on the maximum number of consecutive transitions” that are written to a computer storage device, id. at col. 2, ll. 59–61, and (2) impose a limit on the maxi- mum number of non-transitions, id. at col. 3, ll. 16–17; col. 10, ll. 47–59. These two limitations on bit transitions are embodied in the claims with the ‘j’ constraint limiting the number of consecutive transitions and the ‘k’ constraint limiting the number of consecutive non-transitions. Independent claim 13 states: A method for encoding m-bit binary datawords into n-bit binary codewords in a recorded waveform, where m and n are preselected positive integers such that n is greater than m, comprising the steps of: receiving binary datawords; and producing sequences of n-bit codewords; imposing a pair of constraints (j;k) on the encoded waveform; generating no more than j consecutive transitions of said sequence in the recorded waveform such that j≧2; and generating no more than k consecutive sample pe- riods of said sequences without a transition in the recorded waveform. Case: 21-2057 Document: 40 Page: 4 Filed: 08/11/2022

Id. at col. 10, ll. 47–59. Dependent claim 14 narrows claim 13 with the limitation, “wherein the consecutive transition limit is defined by the equation 2≦j<10.” Id. at col. 10, ll. 60–61. Claim 17 narrows claim 14 with limitations di- rected to an additional format for representing data and transitions. Id. at col. 11, ll. 1–6. Both parties treat claim 17 as standing or falling with claim 14, so we focus only on claim 14. II LSI contends that claim 14 in the ’601 patent is antici- pated by Okada and Tsang. Okada teaches converting in- put data blocks using two rules that eliminate the occurrence of certain patterns in the input data blocks for use with optical disks. Okada, col. 3, ll. 36–68. Okada’s Rule 1 provides, “A pattern after conversion consists of at least one ‘0’ and an even number of consecutive ‘1’.” Id. at col. 3, ll. 64–65. Okada’s Rule 2 provides, “A pattern after conversion includes a section consisting of ‘01010’ and a section consisting of at least one ‘0’ or an even number of consecutive ‘1’.” Id. at col. 3, ll. 66–68. Okada’s Tables 1–9 include an example mapping of all 8-bit input data blocks to 13-bit converted output data blocks based on Okada’s two rules. Id. at col. 4, ll. 1–9. LSI originally contended that Okada’s disclosure of Rule 2 itself anticipates claims 14 and 17 of the ’601 patent, but later argued instead that Tables 8 and 9 were embodiments that anticipate claims 14 and 17. III LSI’s second theory of anticipation relies on Tsang, and particularly those portions of Tsang disclosed earlier in what is known as the Seagate Annual Report. Some back- ground on the ’601 patent is necessary to understand the Tsang anticipation theory. On September 26, 1995, Dr. Moon and Dr. Brickner submitted the Seagate Annual Re- port about MTR coding to Seagate, an industry collaborator on their research. The material in the Seagate Annual Case: 21-2057 Document: 40 Page: 5 Filed: 08/11/2022

LSI CORPORATION v. 5 REGENTS OF THE UNIVERSITY OF MINNESOTA

Report was later embodied in the ’601 patent. It is not clear whether the Seagate Annual Report was publicly available before the ’601 patent’s priority date. In both the Seagate Annual Report and the ’601 patent, Dr. Moon and Dr. Brickner describe MTR coding that takes an input sequence of binary data and encodes or converts it in a way that eliminates error-prone patterns of consec- utive bit transitions before saving or storing the encoded sequence in a computer storage device. See ’601 patent, col. 1, ll. 16–55; col. 2, l. 40–col. 3, l. 17; J.A. 3550–57. MTR coding as described in both the ’601 patent and the Seagate Annual Report includes the two limitations on consecutive bit transitions and non-transitions. ’601 patent, col. 2, ll. 59–61; col. 3, ll. 16–17; col. 10, ll. 47–59; J.A. 3553, 3556. To accomplish the encoding and achieve the two limitations on transitions and non-transitions, the ’601 patent and the Seagate Annual Report describe a “fixed-length block code[]” that maps every 4-bit input data block to a unique 5-bit codeword. ’601 patent, col. 4, l. 61–col. 5, l. 18; see J.A. 3553, 3556–57. MTR coding that maps 4-bit input data blocks to 5-bit codewords is a rate 4/5 code.

Free access — add to your briefcase to read the full text and ask questions with AI

Related

Smithkline Beecham Corp. v. Apotex [Corrected Date]
439 F.3d 1312 (Federal Circuit, 2006)
In Re Derek Anthony Costello and Robert McClean
717 F.2d 1346 (Federal Circuit, 1983)
Allergan, Inc. v. Apotex Inc.
754 F.3d 952 (Federal Circuit, 2014)
Duncan Parking Technologies v. Ips Group, Inc.
914 F.3d 1347 (Federal Circuit, 2019)
Regents of the Univ. of Minn. v. Lsi Corporation
926 F.3d 1327 (Federal Circuit, 2019)

Cite This Page — Counsel Stack

Bluebook (online)
Lsi Corporation v. Regents of the University of Minnesota, Counsel Stack Legal Research, https://law.counselstack.com/opinion/lsi-corporation-v-regents-of-the-university-of-minnesota-cafc-2022.