Livia C. Schmierer and Jacques H. F. Valin v. John C. Newton

397 F.2d 1010, 55 C.C.P.A. 1362
CourtCourt of Customs and Patent Appeals
DecidedOctober 10, 1968
DocketPatent Appeal 7879
StatusPublished
Cited by2 cases

This text of 397 F.2d 1010 (Livia C. Schmierer and Jacques H. F. Valin v. John C. Newton) is published on Counsel Stack Legal Research, covering Court of Customs and Patent Appeals primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Livia C. Schmierer and Jacques H. F. Valin v. John C. Newton, 397 F.2d 1010, 55 C.C.P.A. 1362 (ccpa 1968).

Opinion

ARTHUR M. SMITH, Judge.

This is an appeal by the senior party, Livia C. Schmierer and Jacques H. F. Valin (Schmierer) from a decision of the Board of Patent Interferences, 1 adhered to on reconsideration, awarding priority of the invention set forth in the single count here in issue to appellee, John C. Newton (Newton) the junior party. 2 The sole count originated as *1011 claim 1 of Sehmierer’s United States patent and was copied by Newton for purposes of interference.

Appellants’ arguments here raise issues as to whether the facts of record are legally sufficient on the questions of conception, reduction to practice, and diligence on behalf of Newton to support the conclusion of the board. Newton’s burden was to establish his case by a preponderance of the evidence. As will be further developed, the facts of record require an affirmance of the decision of the board on the question of priority.

The assignees of the respective parties are Societe Nouvelle d’Electronique of Paris, France, for appellants, and International Business Machines Corporation for appellee.

Background of the Invention

The invention relates to a digital computing system which may receive messages of an arithmetical type from a memory. Appellants, in their brief, explain that the invention defined in the count may be described by reference to the operation of a simplified conventional computer.

A digital computing system of the type to which the invention relates processes data in response to and in accordance with a series of instructions. Both the data and the instructions are in the form of binary-coded words which are stored in the memory unit of the computing system. The systems disclosed by Schmierer and by Newton both utilize a message which includes an operation, or instruction, portion and a single-address portion.

Typical computers known to the art at the time the invention here in issue was made included what are known as “single-address” computers. Such single-address computers are capable of performing certain basic arithmetic operations, such as adding and subtracting. A typical adding operation takes the form of a command “Add X” wherein “Add” is termed an instruction word, or operation portion, constituting the functional message part of the coded signal. “X” is a data word constituting the algebraic or address portion of the coded signal which signifies to the computing system where in the memory to find the quantity to be added. Similarly, a subcontraction operation will be in the form of a command “Subtract Y” where, again, “Subtract” is an instruction word and “Y” is a data word.

In the then conventional operation of such a computer, the two commands “Add” and “Subtract” or similarly two “Add” or two “Subtract” commands operated in sequence would require the successive callout of at least two coded signals comprising four different “words” from at least two different memory locations in which they are stored, for example, “Add X” and “Subtract Y.”

These coded signals are withdrawn from the memory of the computer to rest temporarily in an instruction register and are used to instruct a sequencing section of the computing system to perform the specified operation. Thus, in the typical known prior-art computers for the exemplary calculation sequence under consideration, (a) the sequence in the calculator section is established for addition, (b) the location X is then found for the quantity to be added before (c) the next operating sequence in the calculator is set up, and, finally, (d) the second quantity is located at Y.

In this art, this conventional sequence of steps, wherein each step is done independently, is called the “non-overlapped” mode of operation.

*1012 The improvement set forth by the count in issue may be referred to as an “overlapped” mode of operation and involves the simultaneous performance of two steps in the foregoing schedule, i.e., to locate a quantity while the previous calculation is in progress, thus resulting in a more rapid calculation. With “overlap,” a second or auxiliary instruction register is added to the system to receive messages from the storage unit, and to set up operations for the specified calculation from the functional message portion of the instruction. The following sequence of steps is exemplary: (a) the first message, e.g., “Add X”, is “fed” through the auxiliary register and is temporarily held in the main register to perform the addition of “X”; (b) the second message “Subtract Y” is “fed” into the auxiliary register and retained to specify the next operation “Subtract”; (c) during the addition, a message in the storage means is located in response to the functional portion of the message “Subtract”; (d) when the addition is completed, the main register is cleared and “Subtract Y” is transferred from the auxiliary register into the main register while the next message is fed into the auxiliary register. Thus, in step (c) a message is located without waiting for the calculation to end, resulting in “overlap”.

The Count

The sole count in issue states:

1. In a digital computing system having storage means for retaining coded information applied thereto, main instruction-register means connected to receive from said storage means combinations of coded signals constituting functional and algebraic message portions, and a computer adapted to perform calculating operations in response to instructions from said main register means corresponding to an algebraic message portion stored therein, the combination therewith of control means including:

auxiliary instruction-register means connected to receive messages from said storage means;
selector means operative under the control of said auxiliary register means, in the presence of a first message in said main register means and a second message in. said auxiliary means, for identifying a third message in said storage means in response to a functional portion of said second message during performance of a calculating operation by said computer in response to an algebraic portion of said first message; and
signal-responsive means operable by an execution signal from said computer indicative of the completion of a calculating operation for clearing said main register means of said first message and thereafter initiating a transfer of said second message from said auxiliary register means to said main register means and a transfer of said third message from said storage means to said auxiliary register means, thereby enabling said computer to operate on an algebraic portion of said second message during transfer of said third message and identification by said selector means of a further message in said storage means. [Emphasis added.]

In the proceedings below, the appellants raised a question of interpretation of the language of the count.

Free access — add to your briefcase to read the full text and ask questions with AI

Related

Christopher J. Stevens v. Shigeru Tamai
366 F.3d 1325 (Federal Circuit, 2004)
Breuer v. DeMarinis
558 F.2d 22 (Customs and Patent Appeals, 1977)

Cite This Page — Counsel Stack

Bluebook (online)
397 F.2d 1010, 55 C.C.P.A. 1362, Counsel Stack Legal Research, https://law.counselstack.com/opinion/livia-c-schmierer-and-jacques-h-f-valin-v-john-c-newton-ccpa-1968.