Home Semiconductor Corporation v. Samsung Electronics Co., Ltd.

701 F. App'x 1006
Court of Appeals for the Federal Circuit·Decided July 25, 2017·No. 2016-2215·Unpublished·Cited by 1 cases

Opinion

Lourie, Circuit Judge.

Home Semiconductor Corp. (“Home”) appeals from the final written decision of the United States Patent and Trademark Office Patent Trial and Appeal Board (“the Board”) in an inter partes review (“IPR”) *1007 proceeding finding that, inter alia, claims 2 and 9-14 of U.S. Patent 6,146,997 (“the ’997 patent”) are unpatentable as anticipated by U.S. Patent 6,277,720 (“Doshi”). Home Semiconductor Corp. v. Samsung Elecs. Co., No. IPR2015-00460, 2016 Pat. App. LEXIS 7424 (P.T.A.B. Apr. 20, 2016) (“Final Decision”). For the reasons that follow, we reverse.

Background

This appeal primarily involves the meaning of the word “over” in the context of the claims, written description, and figures. Home owns the ’997 patent, which is directed to “a simplified method for forming a self-aligned contact hole,” in which a conductive plug can be formed to electrically connect the semiconductor device to other circuit elements. ’997 patent col. 2 11. 3-4, col. 3 11. 26-31. The ’997 patent first describes the conventional technique of forming a self-aligned contact hole, which involves the separate steps of (1) forming “nitride spacers 22a” by depositing and anisotropically etching “a conformal layer of silicon nitride 22”; and (2) forming the “contact hole 29” after depositing another “conformal layer of etch barrier material 24,” which “serv[es] as an etch stop” and is later partially removed to “expose the diffusion region 18.” Id. col. 1 11. 33-57, figs. 1B-E. The ’997 patent then describes a simplified process that “reduces one etch step and one deposition step as compared to the conventional method.” Id. col. 3 11. 10-42. Instead of two separate steps of forming the nitride spacers and forming the contact hole, each performed after a deposition of respective conformal layers 22, 24, the ’997 patent describes a process involving one “conformal layer of silicon nitride 62,” which is anisotropically etched to “[slimultaneously” form “nitride spacers 62a” and a “contact hole 67.” Id. col. 2 1. 60-col. 31. 25.

In both of the known and simplified processes described in the ’997 patent, “a thin oxide layer” 20, 60 is “formed over the substrate surface and on the sidewalls of the gate electrode” before the conformal layer 22, 62 is deposited, id. col. 111. 29-31, col. 2 11. 55-57 (emphasis added); id. figs. 1A, 2A, and once the thin oxide layer 60 is formed and the conformal layer 62 is deposited, the semiconductor structure at this intermediate stage of the described process appears as below:

[[Image here]]

id. fig. 2B; see also id. fig. 1B. Later, a portion of the thin oxide layer is removed “to expose the diffusion region.” Id. col. 1 ll. 38-40, col. 3 ll. 22-24.

Claim 2 of the ’997 patent reads as follows:

2. The method as claimed in claim 1, further comprising a step of forming an oxide layer over the diffusion region and on the sidewalls of the gate electrode by thermal oxidation prior to forming the barrier layer.

Id. col. 4 11. 5-8 (emphasis added). Claim 9 is an independent claim involving multiple steps and includes a similar step of “forming an oxide layer over the diffusion re *1008 gion and on the sidewalls of the gate electrode by thermal oxidation.” Id. col. 4 11. 32-34 (emphasis added). Claims 10-14 depend from claim 9 and add additional limitations not at issue on appeal,

Samsung Electronics Co., Ltd., Samsung Electronics America, Inc., Samsung Semiconductor, Inc., and Samsung Austin Semiconductor LLC (together, “Samsung”) filed a petition for IPR of the ’997 patent, alleging that claims 1-14 were anticipated by'Doshi, that claims 1 and 3-8 were anticipated by U.S. Patent 5,770,498 (“Becker”), and that claims 2 and 9-14 would have been obvious over Becker and Wong, et al., Process Induced Degradation of Thin Oxides, ULSI Sci. & Tech. (1987). The Board instituted review only on the anticipation ground based on Doshi. Samsung Elecs. Co. v. Home Semiconductor Corp., No. IPR2015-00460, 2015 WL 3430191, at *8 (P.T.A.B. May 27, 2015).

In its patent owner response, Home argued that “forming an oxide layer over the diffusion region” in claims 2 and 9 should mean “forming an oxide layer covering the diffusion region” in light of the specification. J.A. 499 (emphasis added). Based on its proposed construction, Home argued that Doshi did not anticipate the challenged claims.

In reply, as it had done in its IPR petition, Samsung argued that the broadest reasonable interpretation of “forming an oxide layer over the diffusion region” should be “forming an oxide layer above the diffusion region.” J.A. 695-96 (emphasis added). Samsung argued that construing “over” as “covering” was too narrow a reading for a person of ordinary skill in the art and that its argument was supported by Becker, which describes gate electrode structures that do not cover the substrate as being “over” the substrate.

In its final written decision, the Board construed, inter alia, “forming an oxide layer over the diffusion region” in claims 2 and 9 as “forming an oxide layer above the diffusion region,” as proposed by Samsung. Final Decision, 2016 Pat. App. LEXIS 7424, at *15. In rejecting Home’s proposed claim construction, the Board reasoned that Home essentially argued for “over” to be construed as “completely covering” and that the plain meaning of “over” and the specification, which does not use the word “covering,” are consistent with understanding “over” to mean “above.” Id. at *12-14. According to its claim construction, the Board found that all the challenged claims were anticipated by Doshi.

Doshi, entitled “Silicon Nitride Dopant Diffusion Barrier in Integrated Circuits,” is generally directed to “a silicon nitride diffusion barrier layer underlying a planar-izing doped oxide layer” so that “dopant in planarizing insulating films is prevented from diffusing into the active regions of the integrated circuit.” Doshi col. 4 11. 12-14, 21-23. In particular, Doshi describes that “sidewall filaments 11 are formed by first oxidizing the sides of polysilicon layer 22” and that “[a] layer of silicon nitride is then deposited overall, and then etched anisotropically to remove the nitride from flat surfaces, leaving sidewall filaments 11 behind.” Doshi col. 7 11. 58-62. Subsequently, a silicon nitride layer 30 is formed; the resulting semiconductor structure at this intermediate stage is shown below:

*1009 [[Image here]]

Doshi fig. 3a (in part); see also id. fig. 3b (in part).

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Home Semiconductor Corporation v. Samsung Electronics Co., Ltd., 701 F. App'x 1006 (Fed. Cir. 2017).

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