Elbrus International Limited v. Samsung Electronics Co., Ltd.

CourtCourt of Appeals for the Federal Circuit
DecidedJune 27, 2018
Docket17-1855
StatusUnpublished

This text of Elbrus International Limited v. Samsung Electronics Co., Ltd. (Elbrus International Limited v. Samsung Electronics Co., Ltd.) is published on Counsel Stack Legal Research, covering Court of Appeals for the Federal Circuit primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Elbrus International Limited v. Samsung Electronics Co., Ltd., (Fed. Cir. 2018).

Opinion

NOTE: This disposition is nonprecedential.

United States Court of Appeals for the Federal Circuit ______________________

ELBRUS INTERNATIONAL LIMITED, Appellant

v.

SAMSUNG ELECTRONICS CO., LTD., Appellee ______________________

2017-1855 ______________________

Appeal from the United States Patent and Trademark Office, Patent Trial and Appeal Board in No. IPR2015- 01524. ______________________

Decided: June 27, 2018 ______________________

PHILIP P. MANN, Mann Law Group, Seattle, WA, for appellant.

NAVEEN MODI, Paul Hastings LLP, Washington, DC, for appellee. Also represented by STEPHEN BLAKE KINNAIRD, JOSEPH PALYS; JOSEPH JOHN RUMPLER, II, Palo Alto, CA. ______________________

Before REYNA, BRYSON, and HUGHES, Circuit Judges. 2 ELBRUS INT’L LTD. v. SAMSUNG ELECS. CO., LTD.

PER CURIAM. Elbrus International Ltd. appeals from the final writ- ten decision in an inter partes review proceeding in which the Patent Trial and Appeal Board found claims 1, 2, 5, 6, and 9 of U.S. Patent No. 6,366,130 (“the ’130 patent”) to be invalid. Samsung Elecs. Co., Ltd. v. Elbrus Int’l Ltd., No. IPR2015-01524, 2017 WL 379208 (P.T.A.B. Jan. 17, 2017). We affirm. BACKGROUND The ’130 patent, entitled “High Speed Low Power Da- ta Transfer Scheme,” relates to a “high speed and lower power” complementary metal-oxide semiconductor (“CMOS”) data transfer arrangement. The arrangement “includes two active pull up/pull down bus drivers, a differential bus that precharges to a specific voltage level and a latched differential sense amplifier that serves as a bus receiver.” ’130 patent, col. 1, ll. 24–28. Claim 1 is the only independent claim. It recites: 1. A data transfer arrangement comprising: two bus drivers; a voltage precharge source; a differential bus coupled to the bus drivers and to the voltage precharge source; a[n]d a latching sense amplifier coupled to the dif- ferential bus; wherein the latching sense amplifier compris- es: a first stage including a cross-coupled latch coupled to a differential data bus; and an output stage coupled to an output of said first stage; ELBRUS INT’L LTD. v. SAMSUNG ELECS. CO., LTD. 3

wherein the output of the first stage is coupled to an input of the output stage; [and] wherein the differential bus and the differen- tial data bus are precharge[d] to a voltage Vpr be- tween Vdd and ground, where Vpr=K*Vdd, and K is a precharging voltage factor. DISCUSSION I Elbrus argues that the Board adopted an erroneous construction of the claim term “bus.” Adopting Samsung’s proposal, the Board construed “bus” as “one or more conductors that are used for the transmission of signals, data, or power.” Samsung Elecs. Co., 2017 WL 379208, at *3. Elbrus contends that the Board should have adopted its proposed construction, i.e., “a common path along which power or signals travel from one or several sources to one or several destinations.” Id. The meaning of the term “bus” bears on whether Samsung’s lead prior art reference, U.S. Patent No. 5,828,241 (“Sukegawa”), dis- closes a “differential data bus,” as recited in claim 1. Although the Board adopted Samsung’s construction, it concluded that Sukegawa discloses a “differential data bus” under both Samsung’s and Elbrus’s proposed con- structions. Id. at *6–7. Because we find no error in the Board’s conclusion, we need not address Elbus’s argu- ments regarding the proper construction of “bus.” Sukegawa is entitled “Signal Transmission Circuit Providing Amplified Output from Positive Feedback of Intermediate Amplifier Circuit.” It concerns “a type of signal transmission circuit wherein the signal is amplified and transmitted by means of the positive feedback of an intermediate amplifier circuit having input/output shared terminals.” Sukegawa, col. 1, ll. 11–15. 4 ELBRUS INT’L LTD. v. SAMSUNG ELECS. CO., LTD.

As part of its petition, Samsung provided the follow- ing annotated excerpt of figure 1 of Sukegawa:

In the diagram, Samsung identified the differential data bus as the lines associated with nodes N3 and N4 (also labeled C), which connect the transistors 38–41 to the transistors 34 and 35 as well as to CMOS inverters 36 and 37. See Sukegawa, col. 8, ll. 49–53. The Board found that those lines disclosed a differen- tial data bus under both Samsung’s and Elbrus’s proposed constructions. The Board noted that Sukegawa “discloses a ‘signal transmission circuit,’ wherein a signal is trans- mitted to receiver circuit 4 containing output terminals OUT and OUT_.” Samsung Elecs. Co., 2017 WL 379208, at *6 (citing Sukegawa, col. 9, ll. 4–24). Those lines carry electrical signals from the transistors to the inverters, a function that satisfies Samsung’s construction of bus as “one or more conductors that are used for the transmis- sion of signals, data, or power.” Id. (citing Sukegawa, col. 8, ll. 59–64; col. 9, ll. 4–7; col. 9, ll. 14–24). ELBRUS INT’L LTD. v. SAMSUNG ELECS. CO., LTD. 5

The Board also found that the portion of figure 1 iden- tified by Samsung satisfies Elbrus’s construction of “bus.” Citing the figure and expert testimony, the Board found that figure 1 shows “a finite, non-zero distance between transistors 34 and 35 and inverters 36 and 37, respective- ly, and discloses transmitting from one portion of the circuit to another portion.” Id. at *7. From this, the Board concluded that Sukegawa discloses a “bus” even under Elbrus’s construction of “a common path along which power or signals travel from one or several sources to one or several destinations.” Id. We find no error in the Board’s analysis. On appeal, Elbrus argues that Sukegawa’s nodes have “no non-trivial distance” and that there is no “transmission of signals, data, or power” over those lines. Neither argument is persuasive. As to the first, the Board cited testimony from both Samsung’s and Elbrus’s experts that a wire of some length would be needed to connect the transistors and the inverters, even if a person of ordinary skill would have been motivated to minimize the length of the wire. Id. at *6–7. Elbrus’s argument that a “bus” must span a “non-trivial distance” is new on appeal; in any event, it is unpersuasive, as there is nothing in the patent to suggest that the claim language is limited to a bus of a certain minimum length. As to the second argument, Sukegawa’s circuit 4, of which those identified lines are part, is a receiver that plays a role in signal transmission, see Sukegawa, col. 8, l. 49 to col. 9, l. 29, and that those lines therefore carry “signals, data, or power.” In sum, because Sukegawa discloses a “bus” under ei- ther Samsung’s or Elbrus’s construction, we affirm the Board’s conclusion and need not reach Elbrus’s other claim construction arguments. II Elbrus next challenges the Board’s conclusion that claim 1’s limitation of buses that are “precharge[d] to a 6 ELBRUS INT’L LTD. v. SAMSUNG ELECS. CO., LTD.

voltage Vpr between Vdd and ground” would have been obvious in light of Sukegawa and a 1984 article in the IEEE Journal of Solid State Circuits by Nicky Chau- Chun Lu & Hu H. Chao (“Lu”). The article, entitled “Half-VDD Bit-Line Sensing Scheme in CMOS DRAM’s,” describes a sensing scheme in which the bit line is pre- charged to half VDD. The article teaches that “the half-VDD bit-line sensing scheme has several unique advantages, especially for high-performance high-density” CMOS Dynamic Random Access Memory (“DRAM”), “compared to the full-VDD bit-line sensing scheme used for” N-type metal-oxide-semiconductor (“NMOS”) memory arrays or “the grounded bit-line sensing scheme for” P-type metal- oxide-semiconductor (“PMOS”) arrays in CMOS DRAM’s. Elbrus raises two arguments on appeal. First, Elbrus argues that Sukegawa teaches away from precharging the bus to half of the supply voltage, as taught in Lu.

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