Application of John P. Mahony

421 F.2d 742, 57 C.C.P.A. 939

• Court: Court of Customs and Patent Appeals
• Decided: February 26, 1970
• Docket: Patent Appeal 8216
• Status: Published

Opinion

LANE, Judge.

This is an appeal from the decision of the Patent Office Board of Appeals which affirmed the rejection of method claims 19 and 20 in appellant’s application serial No. 243,203, for- “Synchronizing Circuit,” filed December 5, 1962. Apparatus claims have been allowed.

THE DISCLOSURE

Appellant’s application relates to data communication systems and more particularly to circuits and methods for automatically synchronizing a receiver of digital information, such as a digital computer. The smallest unit of information in binary form is conceptualized, in information theory, as a binary digit, or bit. Like numbers and letters, bits are pure abstractions. To transmit the information bits, however, they must be represented in some physical form, as we shall later discuss.

The application discloses a method of synchronizing a receiver with a bit stream containing digital information. The bit stream of appellant’s disclosure is in the form of a sequence of electrical signals, each signal having one of two possible values. These values are designated 1 and 0 for convenience. A certain predetermined number of bits in sequence constitute a digital “word” corresponding to one printed character. In order for the receiving device to “know” where to divide the stream into words, a system of framing is employed, wherein each word consists of a certain number of information bits and a pattern of framing bits. The pattern of framing bits is always of the same value and in the same position relative to the information bits of each word. For example, words might be predetermined to have six bits each, with the first and sixth bits being framing bits of value 1 and 0 respectively, and the second through fifth bits being information bits which may be either l’s or 0’s according to the information they contain. Synchronization is the physical state of the receiver wherein it is set to receive the next bit as the first information bit of a digital word if that bit truly is the first information bit of a word. The receiver is “in sync” when the receiver “knows” where the bit stream should be divided to make words. Let us consider another simple example of framing, where each word is predetermined to consist of four bits, the first bit being the framing bit and the other three being information bits, and the framing bit is always of the same value, such as 1, whereas the information bits may be either l’s or 0’s. While the human mind cannot perceive bits in the form of electrical signals, we may, for the purpose of understanding the invention and the position of the Patent Office, represent a segment of a typical bit stream in visual character . form, as follows: 011000101110. Appellant has disclosed that one way of determining which bits in this stream are framing bits is to perform, by means of digital circuitry, a logical process of elimination. He disclosed a circuit comprising a shift register and various AND and OR circuits arranged to sample sequences of bits, each sequence having a number of bits equal to the number of bits known to be in a word. Of course, for the process to be carried out as disclosed by appellant, the bit stream must be in the form of electrical signals. In our second example, where there are four bits to a word and the framing bit is represented as a 1 at the beginning of each word, the circuit would be designed to sample various groups of four bits in order to determine which positions in the stream could not be framing bits. Appellant’s circuit in such an example would have a four-stage shift register, with each stage initially set at 1. The bit stream is fed through the shift register. A gate circuit is connected between the fourth stage and the input to the first stage. The gate is enabled to receive the next incoming bit if the fourth stage contains a 1. With the gate enabled, the shift register is capable of receiving the next bit as a 1 if it is a 1, but once a 0 occurs in any bit position that position will continue to register a 0 in future se quences. A counter circuit is also provided, which in this case would count 0’s. When three successive 0’s are counted, it logically follows that the next bit will be a 1 and will be the framing bit. When this occurs, a gate to the receiver is enabled and the receiver is set to receive the beginning of a digital word. The disclosure does not show any other means for carrying out the logical process on the bit stream, nor does it suggest that the process could be performed mentally.

THE INVENTION

Both claims on appeal are method claims. Claim 19 is illustrative:

19. The method of establishing which bits in a bit stream are data bits and which are framing bits, where the framing bits appear in predetermined positions and have a predetermined sequence of values, comprising the steps of

(1) comparing to one another the values of bits in respective bit positions in successive equal length groups of bits,

(2) registering which respective positions in said groups of bits have a sequence of bit values inconsistent with said predetermined framing sequence as ascertained by repetitions of the comparing step, and

(3) counting the number of successive bit positions in the bit stream wherein the sequence of bit values has been ascertained as inconsistent with the predetermined framing sequence, whereby the framing bit positions are established when the number of successive bit positions counted is equal to the total number between the framing bit positions.

THE EXAMINER

The examiner rejected the appealed claims under 35 U.S.C. §§ 100 and 101 as being drawn to nonstatutory subject matter. He considered purely mental processes to be nonstatutory and regarded the claims as defining a purely mental process. The examiner demonstrated how the claimed process could be performed mentally based upon his understanding of • the terms in the claims. His position may be demonstrated by returning to our above example where a portion of the bit stream was represented as 011000101110, it being known that there are four bits to a word and that the first bit is a framing 1. The examiner would perform the elimination process by breaking the representation of the stream arbitrarily into groups of four bits each: 0110 0010 1110. In each group the first position is examined; it is seen to be not always a 1 and hence cannot be the framing position. The same can be seen regarding the second and fourth positions. The conclusion is that the third position must be the framing position. It is therefore known that in the portion of the bit stream represented, a word begins with the third, seventh and eleventh bits. While this knowledge might not be usable to any practical advantage, it was the examiner’s view that the claimed process had been performed.

THE BOARD

The board agreed with the examiner’s reasons and affirmed the rejection of the appealed claim under 35 U.S.C. §§ 100, 101. In addition, the board mentioned section 112, saying:

We find the Examiner’s position convincing that appellant’s claims are required to particularly point out and distinctly claim the invention (35 U. S.C. 112) and a claim which embraces within its scope that which cannot be patented is not in conformity with the statute.

The examiner had not made a rejection under 35 U.S.C. § 112 and it is not clear from the above language that the board did so. However, both parties have treated the case before us as containing a section 112 rejection, and we shall so regard it.

APPELLANT

Appellant contends that the claimed process cannot be “purely mental” since nonmental means are disclosed for carrying it out. He cites footnote 22 of this court’s opinion in In re Prater, 415 F.2d 1393, 56 CCPA 1381, (1969). Appellant argues that the “bit stream” referred to in the preamble would be known by persons skilled in the art to mean only a sequence of bits in electrical signal form. Similarly, he argues, the “bits” referred to in each step would be interpreted in the art to mean only bits in electrical signal form. Since electrical signals cannot be operated upon in the mind, appellant concludes that it would be an unreasonable construction of the claims to view them as covering any process implemented mentally. He further points out that since his disclosure pertains to a bit stream in electrical signal form only, and in no way suggests mental acts, there is no basis for construing the terms of the claim as having other than their normal meaning in the art.

As to the section 112 rejection, appellant argues that his above construction of the claims meets the objection that they fail to point out the invention, since he intends to cover only the machine-implemented process, and not any mentally implemented process, and' by his construction the claims do exactly that. To further support this view, appellant calls attention to the third paragraph of section 112, which reads:

An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. (Emphasis ours.)

Appellant concludes that since his specification mentions only machine-implemented acts, the third paragraph of section 112 prevents construction of the claim to cover mental implementation of the process. Our decision makes it unnecessary to pass on this point.

OPINION

It should first be noted that there is no dispute in this case regarding the statutory nature of the invention disclosed. The disclosure shows a process for operating on bits in electrical signal form. Such an operation cannot be done in the mind. Appellant’s disclosure is clearly a contribution to the automatic data processing art.

The issue is solely with regard to interpretation of the claims. Both sides in this case have assumed that if a claim reads on both mental and nonmental implementation of a process, the claim is drawn to nonstatutory subject matter. We refrained from deciding that question in Prater, supra, and we decline to decide it here. We shall assume, as appellant has, that such a claim would be nonstatutory under 35 U.S.C. § 101.

We first consider the rejection under 35 U.S.C. § 112. The board expressed the view, in the language quoted above, that where a claim reads on both statutory and nonstatutory subject matter it could not be in compliance with the second paragraph of section 112. With this view we disagree. That paragraph, as quoted above, requires that an applicant distinctly claim what he regards as his invention. To inject any question of statutory subject matter into that paragraph is to depart from its wording and to complicate the law unnecessarily. The proper consideration here is whether the appealed claims cover only what appellant regards as his invention. Appellant, through counsel, has said at several points in this case that he intends the claims to cover only the machine implementation of the process and not the mental implementation thereof. If the appealed claims accomplish that intent, not only will appellant have overcome the § 112 rejection, but he will also have overcome the § 101 rejection, since the machine-implemented process is clearly statutory. This question of what the claims reasonably cover is therefore dispositive of the case before us.

We agree with appellant that the words “bit” and “bit stream,” as used in the claims and understood in the art, render mental performance of the claimed process impossible. To determine what these terms mean in the computer or data processing art, appellant refers us to Computer Dictionary and Handbook (1966) by Charles J. Sippl, wherein the following appears:

bit stream — This is a term used regularly in conjunction with transmission methods in which character separation is accomplished by the terminal equipment, and the bits are transmitted over the circuit in a consecutive line of bits.

The solicitor, at oral argument, urged that this meaning might not be the only meaning known in the art, but the Patent Office, with an enormous technical library available to its personnel, has not asserted any other meaning given to these terms in the art, and has not referred us to any authority indicating any other meaning. We have looked further, since the matter is one of which we are asked to take judicial notice.. We found, in Condensed Computer Encyclopedia (1969), edited by Philip B. Jor-dain and Michael Breslau, the following:

bit A binary digit. The term is an abbreviation for Binary digiT. In computers, a bit is- represented by a pulse (1) or the absence of a pulse (0).

The above definitions lead us to conclude that in computers bits appear in the physical form of pulses or the absence of pulses, and that the presence or absence of a pulse is in turn represented by the characters 1 and 0. We further conclude that if the bits are in a bit stream, as required by the claims here and understood in the data transmission art, the bits must have the form of electrical pulses, so that they can be transmitted “over the circuit” according to the Sippl definition. The examiner’s example, therefore, is a process for operating not on bits in a bit stream as required by the claims, but rather on a character representation of a bit stream, which is no more a bit stream than a drawing of a sinusoid is a sinusoidal electrical signal. Many electrical operations are expressed in terms which have one meaning in .the art and quite a different meaning generally. Thus, the art speaks of clipping, clamping, chopping, rectifying, filtering, and so on, with reference to electrical signals. 1 No one in the art would give these terms their general colloquial meaning when discussing technical matters with other persons skilled in the art. To do so would be absurd. Similarly here, once we know that “bit stream” in the art means a sequence of electrical signals or pulses, it would be absurd to say that the claims reasonably read on a mentally implemented process. We are aware of no way in which the human mind can operate on such signals. Moreover, the Sippl definition states that character separation, i. e., separation of digital words, is accomplished by the terminal equipment, not by the human mind. We therefore must conclude that appellant’s construction of the claims is a reasonable construction, and that the broad construction urged by the Patent Office is not reasonable.

The present case is distinguishable from Prater, supra. In that case the process disclosed involved primarily the manipulation of a series of mathematical equations to facilitate efficient spectral analysis. Machine implementation of the process was contemplated by the disclosure and was particularly desirable due to the large number of manipulations required. The claims, however, had no explicit language indicating that only protection of a machine-implemented process was sought, and the court did not find that any terms used in the claims had such meaning in the art as to implicitly limit the scope of the claims to machine implementation. Thus, giv ing the Prater claims their “broadest reasonable interpretation consistent with the specification,” as this court feels obliged to do for reasons stated in Prater, it was concluded that they did encompass performing the recited manipulations mentally with the possible aid of pencil and paper. Since the appellants in Prater regarded as their invention only the machine-implemented process, their claims were held unpatentable under the second paragraph of § 112. In the process here claimed, there is again no express reference to a machine-implemented or nonmental process. However, we have found that the term “bit” when used in conjunction with “bit stream” has a meaning in the art which precludes reading the claims on a mentally performable process.

The decision of the board is reversed.

Reversed.

1 . See, e. g., Markus, Electronics and Nucleonics Dictionary, 3rd ed. (1966).