Viasat, Inc. v. Western Digital Technologies, Inc.

CourtCourt of Appeals for the Federal Circuit
DecidedJanuary 7, 2026
Docket24-1483
StatusUnpublished

This text of Viasat, Inc. v. Western Digital Technologies, Inc. (Viasat, Inc. v. Western Digital Technologies, Inc.) is published on Counsel Stack Legal Research, covering Court of Appeals for the Federal Circuit primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Viasat, Inc. v. Western Digital Technologies, Inc., (Fed. Cir. 2026).

Opinion

Case: 24-1483 Document: 45 Page: 1 Filed: 01/07/2026

NOTE: This disposition is nonprecedential.

United States Court of Appeals for the Federal Circuit ______________________

VIASAT, INC., Appellant

v.

WESTERN DIGITAL TECHNOLOGIES, INC., Appellee ______________________

2024-1483 ______________________

Appeal from the United States Patent and Trademark Office, Patent Trial and Appeal Board in No. IPR2022- 01171. ______________________

Decided: January 7, 2026 ______________________

MATTHEW R. FORD, Bartlit Beck LLP, Chicago, IL, ar- gued for appellant. Also represented by MEG E. FASULO, NEVIN M. GEWERTZ, JOHN SCOTT MCBRIDE, RAVI SHAH; NOSSON KNOBLOCH, Denver, CO; DAVID ZIMMER, Zimmer, Citron & Clarke LLP, Cambridge, MA.

BRIAN M. BUROKER, Gibson Dunn & Crutcher, LLP, Washington, DC, argued for appellee. Also represented by NATHAN ROBERT CURTIS, Dallas, TX; L. KIERAN KIECKHEFER, San Francisco, CA. Case: 24-1483 Document: 45 Page: 2 Filed: 01/07/2026

______________________

Before CHEN, BRYSON, and CUNNINGHAM, Circuit Judges. BRYSON, Circuit Judge. In this appeal from a final written decision of the Pa- tent Trial and Appeal Board, the patentee, Viasat, Inc., (“Viasat”) challenges the Board’s decision that certain claims of Viasat’s patent-in-suit are unpatentable for obvi- ousness. We hold that substantial evidence supports the Board’s obviousness decision, and we therefore affirm. I Viasat is the owner of U.S. Patent No. 8,966,347 (“the ’347 patent”), titled “Forward Error Correction with Paral- lel Error Detection for Flash Memories.” The patent is di- rected to methods and systems for error correction in data retrieved from flash memory. Because flash memory is prone to an increasing error rate in the data over time, the invention is designed to modify the error correction process to make it more robust as the number of errors in the stored data begins to climb. One method for correcting errors in flash memory data is to use a technique referred to as forward error correction (“FEC”), which generally uses an error correction code (“ECC”) to generate and store redundant information alongside the original data. When the original data is re- trieved from memory, it is compared against the redundant information, which enables the system to detect and ulti- mately correct the corrupted data. Case: 24-1483 Document: 45 Page: 3 Filed: 01/07/2026

VIASAT, INC. v. WESTERN DIGITAL TECHNOLOGIES, INC. 3

System claims 13 through 23 of the ’347 patent are at issue in this case. 1 Independent claim 13 is representative. It reads as follows: 13. A system comprising: [a] an encoder to encode data using forward error cor- rection coding; [b] a flash memory to store the encoded data; [c] a decoder to retrieve the encoded data stored in the flash memory to generate a data stream, and [d] to process the data stream to correct errors in the data stream asso- ciated with the flash memory using at least a first error correction sub-module; and [e] a controller to: monitor a metric of the flash memory while repeat- ing the encoding, the storing, the retrieving and the processing, wherein the metric represents memory per- formance degradation of the flash memory; [f] determine that the monitored metric exceeds a threshold; [g] in response to the determination, modify the for- ward error correction coding for use by the encoder in subsequently encoding data for storage in the flash memory; and [h] in response to the determination, powering-up, from an inactive mode, a second error correction sub- module arranged in parallel with the first error

1 The PTAB also found method claims 1–11 to be un- patentable, but Viasat has not appealed the PTAB’s deci- sion with respect to those claims. Case: 24-1483 Document: 45 Page: 4 Filed: 01/07/2026

correction sub-module for subsequent data stream pro- cessing. 2 ’347 patent, col. 11, line 40, through col. 12, line 10. For present purposes, the critical portions of claim 13 are limitations 13[c] and 13[d], which describe the function of the decoder as being “to retrieve the encoded data stored in the flash memory to generate a data stream, and to pro- cess the data stream to correct errors in the data stream associated with the flash memory using at least a first er- ror correction sub-module.” Id., col. 11, ll. 44–48. II Western Digital Technologies, Inc., (“Western Digital”) filed a petition for inter partes review of claims 1 through 11 and 13 through 23 of the ’347 patent. The Patent Trial and Appeal Board granted the petition, and in its final written decision the Board found all the challenged claims to be unpatentable for obviousness. J.A. 1. In so finding, the Board relied on prior art published patent applications to Diggs and Cheng. 3 While the Board relied on combina- tions of Diggs and Cheng for the disclosure of certain limi- tations, its decision found that the 13[c] and 13[d] limitations at issue on appeal were disclosed by Diggs alone, and thus only Diggs is relevant to our analysis here. J.A. 29–32.

2 In its briefing before the Board, Western Digital added the bracketed letters to the claims to facilitate anal- ysis, and Viasat relied on these same letter assignments in its appellate brief. The claims are reproduced here includ- ing the bracketed letters employed by the parties and the Board. 3 The Diggs reference is Pub. No. US 2009/0070651; the Cheng reference is Pub. No. US 2009/0276570. Case: 24-1483 Document: 45 Page: 5 Filed: 01/07/2026

VIASAT, INC. v. WESTERN DIGITAL TECHNOLOGIES, INC. 5

Diggs is directed to a system for adjustable error cor- rection in solid-state storage systems, such as flash memory storage. Diggs ¶¶ 2, 4, 7–8, J.A. 451. The Diggs system is very similar to the invention recited in the ’347 patent, in that the Diggs system, like the patented system, uses a controller and a decoding device to retrieve signals from the solid-state memory, to decode those signals, and to detect and correct the errors in the data revealed by the error correction mechanism. In the portion of its decision pertinent to the issue pre- sented in this appeal, the Board addressed Western Digi- tal’s argument that the “decoder” recited in claim 13 of the ’347 patent is disclosed by the Diggs Controller. The Board noted that figure 1 of Diggs, which depicts an embodiment of the Diggs invention, shows that Diggs contains a Con- troller, designated as component 114. The Controller in- corporates the ECC Detection and Correction module, which is designated as component 125. Diggs ¶ 23, J.A. 452. Figure 1 of Diggs, J.A. 447, is depicted below. Case: 24-1483 Document: 45 Page: 6 Filed: 01/07/2026

In the proceedings before the Board, the parties fo- cused on whether Diggs teaches a “decoder” that both “re- trieve[s] the encoded data stored in the flash memory to generate a data stream,” as recited in claim element 13[c] of the ’347 patent, and also “process[es] the data stream to correct errors in the data stream,” as recited in claim ele- ment 13[d] of the patent. The parties agreed that the component denominated “Controller” in Diggs (component 114) performs the func- tion of retrieving the encoded data to generate a data stream, and that the component denominated “ECC Detec- tion and Correction” in Diggs (component 125) performs the function of processing the data stream to correct errors. J.A. 30–31. The parties disagreed, however, about whether that meant that the component in Diggs that performs the retrieval function is separate from the component that per- forms the error correction function.

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