Semiconductor Energy Laboratory Co. v. Chi Mei Optoelectronics Corp.

485 F. Supp. 2d 1089, 2007 U.S. Dist. LEXIS 28926, 2007 WL 1174823
CourtDistrict Court, N.D. California
DecidedApril 19, 2007
DocketC 04-04675 MHP
StatusPublished

This text of 485 F. Supp. 2d 1089 (Semiconductor Energy Laboratory Co. v. Chi Mei Optoelectronics Corp.) is published on Counsel Stack Legal Research, covering District Court, N.D. California primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Semiconductor Energy Laboratory Co. v. Chi Mei Optoelectronics Corp., 485 F. Supp. 2d 1089, 2007 U.S. Dist. LEXIS 28926, 2007 WL 1174823 (N.D. Cal. 2007).

Opinion

MEMORANDUM & ORDER

PATEL, District Judge.

Plaintiff Semiconductor Energy Laboratory Company Ltd. (“SEL”) brought this *1094 patent infringement action against defendant Chi Mei Optoelectronics Corp. (“CMO”) et al., alleging infringement of four United States patents related to in situ DNA hybridization. Three patents in suit currently remain. Now before the court are CMO’s motions for summary judgment of noninfringement and invalidity as to the asserted claims of all three patents. Having considered the parties’ arguments and submissions, and for the reasons set forth below, the court enters the following memorandum and order.

BACKGROUND

An overview of LCD technology and summaries of the asserted patents are provided in this court’s Claim Construction Order. Docket Entry 111 at 1-6 (hereinafter “Claim Construction Order”). The claims at issue in these motions are summarized below.

I. U.S. Patent No. 6,756,258

SEL alleges that CMO’s method of manufacturing thin film transistors (“TFTs”) for inclusion in certain LCD products infringes claims 3-6, 10-13 and 18-21 of the U.S. Patent No. 6,657,258 (“the '258 Patent”). Claim 3 of the patent claims:

A method of manufacturing a semiconductor device comprising the steps of: forming a gate electrode on an insulating surface;
forming a gate insulating film comprising silicon nitride on said gate electrode; forming a first semiconductor film comprising amorphous silicon over said gate electrode with said gate insulating interposed therebetween; forming a second semiconductor film on said first semiconductor film, said semiconductor doped with an N-type dopant; patterning said first and second semiconductor films;
forming a conductive layer on the patterned second semiconductor film; patterning the conductive layer to form source and drain electrodes by using a mask wherein a portion of the patterned second semiconductor film is exposed between said source and drain electrodes;
etching the exposed portion of the second semiconductor film to form source and drain regions wherein a channel forming region is formed in said first semiconductor film between said source and drain regions;
wherein said conductive layer is over-etched to form a stepped portion from an upper surface at the source and drain electrodes to the surface at the first semiconductor film.

Claims 4-6 recite the same steps as Claim 3 with the exception of the final element, though the final element of each of these claims includes the limitations “stepped portion” and “upper surface.” Id. ¶¶ 15-17. Claims 10-13 depend from claims 3-6, respectively, and further require that the gate electrode “comprises a material selected from the group consisting of chromium, aluminum and tantalum.” Claims 18-21 also depend from claims 3-6, respectively, and further require that “the first semiconductor film comprises intrinsic amorphous silicon.” Each of the asserted claims, therefore, contains the “upper surface” limitation.

II. U.S. Patent No. 6,^0^80

CMO seeks summary judgment of non-infringement and invalidity as to claims 1, 2, 4, 5, 11, 12, 14 and 15 of U.S. Patent No. 6,404,480 (“the '480 Patent”). Claims 1 and 11 are independent claims. Claim 1 claims:

An active matrix display device comprising:
a first substrate;
a first interlayer insulating film provided over said first substrate; *1095 a first conductive film provided on said first interlayer insulating film;
a second interlayer insulating film provided on said first conductive film, said second interlayer insulating film having at least two openings;
a second conductive film provided on said second interlayer insulating film and in said openings;
a second substrate opposed to said first substrate;
a third conductive film provided on said second substrate; and
a plurality of conductive spacers held between said first substrate and said second substrate;
wherein said first conductive film is connected with said second conductive film in said openings;
wherein at least one of said conductive spacers is held over said second inter-layer insulating film and in contact with both said second conductive film and said third conductive film.

Claims 2, 4 and 5 depend from Claim 1.

Claim 11 claims:
An active matrix display device comprising:
a first substrate;
a first interlayer insulating film provided over said first substrate;
a first conductive film provided on said first interlayer insulating film;
a second interlayer insulting film provided on said first conductive film, said second interlayer insulating film having at least two openings;
a second conductive film provided on said second interlayer insulating film and in said openings;
a second substrate opposed to said first substrate;
a third conductive film provided on said second substrate; and
a plurality of conductive spacers held between said first substrate and said second substrate;
wherein said first conductive film is connected with said second conductive film in said openings;
wherein at least one of said conductive spacers is held over said second inter-layer insulating film and in contact with both said second conductive film and said third conductive film;
wherein each of said openings occupies an area larger than the area occupied by each of said conductive spacers.

Claims 12, 14 and 15 depend from Claim 11.

III. U.S. Patent No. í, 691,995

CMO claims that claims 22-30, 40, 41, 53-58 and 62-67 of U.S. Patent No. 4,691,-995 (“the '995 Patent”) are invalid and/or not infringed by CMO’s manufacturing process. Each of the asserted claims requires “a step of making a sealing structure on the periphery of the first and second substrates.” JSUF ¶ 4. The court previously construed this limitation in connection with the application of a thermo-setting resin to join the two substrates prior to the formation of the sealing structure. See Claim Construction Order at 35-37. CMO’s accused devices are formed by applying a thermosetting and UV curable resin to one substrate before pressing an opposing substrate into contact with the resin. JSUF ¶ 17.

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485 F. Supp. 2d 1089, 2007 U.S. Dist. LEXIS 28926, 2007 WL 1174823, Counsel Stack Legal Research, https://law.counselstack.com/opinion/semiconductor-energy-laboratory-co-v-chi-mei-optoelectronics-corp-cand-2007.