Nazomi Communications, Inc. v. Arm Holdings, Plc

403 F.3d 1364, 74 U.S.P.Q. 2d (BNA) 1458, 2005 U.S. App. LEXIS 5868, 2005 WL 820491
CourtCourt of Appeals for the Federal Circuit
DecidedApril 11, 2005
Docket2004-1101
StatusPublished
Cited by125 cases

This text of 403 F.3d 1364 (Nazomi Communications, Inc. v. Arm Holdings, Plc) is published on Counsel Stack Legal Research, covering Court of Appeals for the Federal Circuit primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Nazomi Communications, Inc. v. Arm Holdings, Plc, 403 F.3d 1364, 74 U.S.P.Q. 2d (BNA) 1458, 2005 U.S. App. LEXIS 5868, 2005 WL 820491 (Fed. Cir. 2005).

Opinion

RADER, Circuit Judge.

The United States District Court for the Northern District of California granted partial summary judgment in favor of ARM Holdings, PLC, ARM Limited, and ARM, Inc. (collectively ARM), finding that ARM’s accused product did not infringe Nazomi Communications, Inc.’s (Nazomi’s) U.S. Patent No. 6,332,215 (the ’215 patent). Nazomi Communications, Inc. v. Arm Holdings, PLC, No. C 02-02521 (N.D.Cal. Sept. 30, 2003). Because the district court did not construe the disputed claim term in sufficient detail for appellate review, this court vacates and remands.

I.

The ’215 patent generally claims “a Java hardware accelerator which can be used to quickly translate Java bytecodes into native instructions for a central processing unit (CPU).” ’215 patent, col. 2, II. 3-6. In computer programming, a series of translations occurs between what is written by a human programmer, and the program that is actually executed by the computer hardware. This appeal focuses on one of these translations, described below.

Sun Microsystems developed a programming language called Java. ’215 patent, col. 1, II. 5-10. In the Java environment, a programmer writes source code in the Java language. This source code is then compiled into Java bytecodes, “instructions that look like machine code, but aren’t specific to any processor.” Id., col. 1, II. 26-28. All types of processors can recognize Java bytecodes if appropriate bytec-ode interpreters are provided.

Two types of memory organization are used to store information in computers. Stack-based memories store information on a last-in, first-out basis. This approach is analogous to a stack of papers in an inbox. To access a paper at the bottom of the stack, a reader must first remove all of the papers above it. Register-based memories, on the other hand, store and retrieve data according to the exact location of each data item, much like an arrangement of post office boxes. Under the analogy, the reader simply identifies and finds the “box” that contains the desired data, which can be instantly retrieved. Java bytecodes are written for computers that use a “stack-based” approach, whereas most modern processors use a “register-based” approach. Translation of Java bytecodes into a form usable by register-based processors requires translation of Java bytec-odes into the “native instructions” of a register-based processor.

In a given machine, either hardware, software, or a combination of the two may perform the translation from stack-based to register-based instructions. One prior art solution for this problem used only software, a Java Virtual Machine (JVM), to perform the translation. JVMs, however, add processing steps and reduce overall execution speed. Seeking to minimize these disadvantages in the prior art, the ’215 patent discloses a hardware Java accelerator that translates stack-based Java bytecode instructions into register-based “native” instructions that are usable by a register-based processor.

Of the asserted claims, claim 1 is representative:

A system comprising:
a central processing unit having a register file, the central processing unit *1367 adapted to execute register-based instructions; and a hardware unit associated with the central processing unit, the hardware unit adapted to convert stack-based instructions into register-based instructions, wherein a portion of the operand stack is stored in the register file of the central processing unit and wherein the hardware unit is adapted to produce at least one of overflow or underflow indications for the portion of the operand stack stored in the register file, wherein the hardware unit is adapted to swap parts of the operand stack in and out of the register file from a memory, the system including an indication of the depth of the portion of operand stack, wherein a[n] overflow or underflow produces an operand transfer between the register file in the central processing unit and memory.

Id., col. 7, II. 24-41 (emphasis added).

In the proceedings below, the parties disputed the meaning of the term “instruction.” Nazomi proposed a broad definition of “instruction” as a command that specifies or causes performance of an operation or function. ARM more narrowly proposed, inter alia, that an “instruction” is “provided to the processor at its input and thus must be recognizable to the decoder.” ARM further made a distinction between “instructions” and “control signals” which, it asserted, are the signals generated by the processor’s decoder that control downstream hardware.

Although not fully persuaded by ARM’s narrow proposal for “instruction,” the district court nevertheless construed “the terms of the patent claims as calling for a hardware unit or subunit that converts stack-based instructions into the register-based instructions prior to the processing of those instructions by the processor in the so-called ‘decode stage.’ Nazomi, slip op. at 6 (emphasis added). Without analyzing the accused product in the light of this construction, the district court reached the conclusion that ARM’s accused device did not infringe the ’215 patent either literally or under the doctrine of equivalents. 1 Id., slip op. at 7.

II.

Here, the district court found that, based upon its claim construction, there could be no genuine issue that ARM’s product did not infringe the ’215 patent, and granted summary judgment. This court reviews grants of summary judgment without deference. Conroy v. Reebok Int’l Ltd., 14 F.3d 1570, 1575 (Fed.Cir.1994). A summary judgment motion is proper if there are no genuine issues of material fact, while viewing the facts in a light most favorable to the non-moving party. See Fed.R.Civ.P. 56(c); Celotex Corp. v. Catrett, 477 U.S. 317, 322, 106 S.Ct. 2548, 91 L.Ed.2d 265 (1986). A finding of infringement, whether literal or by equivalents, is a question of fact. Bai v. L & L Wings, Inc., 160 F.3d 1350, 1353 (Fed.Cir.1998). The district court’s claim construction, a matter of law on appeal, receives no deference from this court. Cybor Corp. v. FAS Techs., Inc., 138 F.3d 1448, 1454 (Fed.Cir.1998) (en banc).

Infringement is a two-step inquiry, in which a court must first construe disputed claim terms, and then compare the properly construed claims to the ac *1368 cused device. Cybor Corp., 138 F.3d at 1454. The patent’s intrinsic record is the primary tool to supply the context for interpretation of disputed claim terms. Vitronics Corp. v.

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403 F.3d 1364, 74 U.S.P.Q. 2d (BNA) 1458, 2005 U.S. App. LEXIS 5868, 2005 WL 820491, Counsel Stack Legal Research, https://law.counselstack.com/opinion/nazomi-communications-inc-v-arm-holdings-plc-cafc-2005.