Monterey Research, LLC v. Stmicroelectronics, Inc.

Court of Appeals for the Federal Circuit·Decided October 26, 2023·No. 22-1411·Unpublished

Opinion

Case: 22-1411 Document: 70 Page: 1 Filed: 10/26/2023

NOTE: This disposition is nonprecedential.

United States Court of Appeals for the Federal Circuit ______________________

MONTEREY RESEARCH, LLC, Appellant

v.

STMICROELECTRONICS, INC., Appellee ______________________

2022-1411, 2022-1770 ______________________

Appeals from the United States Patent and Trademark Office, Patent Trial and Appeal Board in Nos. IPR2020- 00990, IPR2020-01491, IPR2021-00704, IPR2021-00776. ______________________

Decided: October 26, 2023 ______________________

KAYVAN B. NOROOZI, Noroozi PC, Los Angeles, CA, ar- gued for appellant.

THERESA H. NGUYEN, Perkins Coie LLP, Seattle, WA, argued for appellee. Also represented by TYLER R. BOWEN, CHAD S. CAMPBELL, Phoenix, AZ; PHILIP ALCIDE MORIN, San Diego, CA. ______________________

Before DYK, TARANTO, and CHEN, Circuit Judges. Case: 22-1411 Document: 70 Page: 2 Filed: 10/26/2023

Opinion for the court filed by Circuit Judge CHEN. Opinion dissenting in part and concurring in part filed by Circuit Judge DYK. CHEN, Circuit Judge. Monterey Research, LLC (Monterey) appeals the Pa- tent Trial and Appeal Board’s (Board) final written deci- sions determining all challenged claims of U.S. Patent No. 6,534,805 (’805 patent) unpatentable. Advanced Micro Devices, Inc. v. Monterey Rsch., LLC, No. IPR2020-00990, 2021 WL 6339618 (P.T.A.B. Nov. 23, 2021) (990 Decision); Qualcomm Inc. v. Monterey Rsch., LLC, No. IPR2020- 01491, 2022 WL 682743 (P.T.A.B. Mar. 4, 2022) (1491 De- cision). Because substantial evidence supports the Board’s findings and we disagree with Monterey’s claim construc- tion argument, we affirm both decisions. BACKGROUND The ’805 patent is directed to “an improved Static Ran- dom Access Memory (SRAM) cell design and method of manufacture.” ’805 patent col. 1 ll. 7–10. The parties’ dis- putes concern, inter alia, claim 8, which reads: A memory cell comprising: a plurality of substantially oblong active regions formed in a semiconductor sub- strate and arranged substantially in paral- lel with one another, and a plurality of substantially oblong local in- terconnects above said substrate that ex- tend only partially across the memory cell and are arranged substantially in parallel with one another and substantially perpen- dicular to said active regions; and Case: 22-1411 Document: 70 Page: 3 Filed: 10/26/2023

MONTEREY RESEARCH, LLC v. STMICROELECTRONICS, INC. 3

a single local interconnect layer comprising local interconnects corresponding to bit- lines and a global wordline. Id. at claim 8. The ’805 patent describes a memory cell with multiple layers of material containing circuit components. 1491 De- cision, 2022 WL 682743, at *2. Local interconnects are short runs that connect features within a circuit, such as bitlines or a global wordline. ’805 patent col. 11 ll. 18–21, col. 13 ll. 12–13, 31–32. Figure 3 of the ’805 patent shows a top-down view of a single local interconnect layer as claimed in the final limitation of claim 8:

Id. at Fig. 3. Local interconnects 38 and 39 correspond to bitlines and are each associated with a single contact re- gion (i.e., regions 16c and 15c). Id. at col. 13 ll. 12–14. Lo- cal interconnects 43 and 44 correspond to a global wordline are also each associated with a single contact region (i.e., regions 17c1 and 17c4). Id. at col. 13 ll. 31–32. At the Board, the parties disputed the meaning of the last limitation in claim 8—“a single local interconnect layer comprising local interconnects corresponding to bitlines and a global wordline.” 1491 Decision, 2022 WL 682743, at Case: 22-1411 Document: 70 Page: 4 Filed: 10/26/2023

*7. 1 While the parties agreed the claimed “single local in- terconnect layer” must contain local interconnects for both bitlines and a global wordline, they disagreed on whether the limitation is further limited. Id. Monterey argued that during prosecution the applicant limited the meaning of the disputed limitation to the embodiment in Figure 3, which, according to Monterey, requires a specific routing of signals laterally (i.e, horizontally) along the claimed local interconnects corresponding to the bitlines and global wordline. Id.; see also id. at *17 (“[T]he arguments are based on Patent Owner’s proposed construction of ‘a single local interconnect layer,’ which requires routing all signals laterally along the interconnect layer.”). Petitioner argued “neither the claim language nor the Specification support Patent Owner’s proposed construction because neither uses the word ‘routing’” and “Figure 3 does not ‘illustrate any routing along the local interconnect layer’ because the ’805 patent does not ‘illustrate any contacts atop the local interconnect layer, let alone specific positions that would demonstrate routing.’” Id. (quoting J.A. 10134). The Board agreed with Petitioner and construed the term to mean “one conductive layer containing non-global interconnects, including interconnects for bitlines and a global wordline, that exclusively performs the function of connecting features within a circuit.” Id. at *8. The Board concluded neither the specification nor prosecution history “limit[s] the single local interconnect layer limitation in the manner Patent Owner contends” because “although Figure 3 shows bitline signals can be routed horizontally . . . nei- ther the Specification nor claims require such routing.” Id. The Board further held the prosecution history does not disclaim any specific routing and instead disclaims the

1 Citations in this section are to the 1491 Decision. The Board’s construction and Monterey’s proposed con- struction in the 990 Decision were the same. Case: 22-1411 Document: 70 Page: 5 Filed: 10/26/2023

MONTEREY RESEARCH, LLC v. STMICROELECTRONICS, INC. 5

location of local interconnects in different layers of the cell. Id. According to the Board, the prosecution history shows Monterey distinguished the claimed memory cell over the prior art memory cell because the claimed memory cell lim- its the local interconnects corresponding to the bitlines and the global wordline to a single layer while the local inter- connects in the prior art were found in multiple layers. Id. Thus, the Board agreed with Monterey that the disputed limitation restricts the local interconnects corresponding to the bitlines and the global wordline to one layer in the cell but declined to adopt Monterey’s additional limitation of a specific lateral routing of signals along these local intercon- nects. The Board also found the prior art reference Oh 2 dis- closed “substantially oblong active regions.” Monterey pri- marily argued Oh’s figures fail to provide precise dimensions for the active regions shown. Id. at *13. The Board disagreed, finding “Petitioner [did] not rely on Fig- ure 3 to demonstrate the precise dimensions of Oh’s active regions. Instead, Petitioner relie[d] on Figure 3 to show the active regions have a ‘substantially oblong’ shape.” Id. (cit- ing J.A. 5024–26). The Board found Oh disclosed the gen- eral shapes of the illustrated active regions such that it taught the limitation. Id. Monterey appeals. We have jurisdiction under 28 U.S.C. § 1295(a)(4)(A). DISCUSSION “We review claim construction de novo and review any subsidiary factual findings based on extrinsic evidence for substantial evidence.” Kyocera Senco Indus. Tools Inc. v. Int’l Trade Comm’n, 22 F.4th 1369, 1378 (Fed. Cir. 2022). We generally give terms “their plain and ordinary mean- ing, which is the meaning one of ordinary skill in the art

2 U.S. Patent No. 6,417,549. Case: 22-1411 Document: 70 Page: 6 Filed: 10/26/2023

would ascribe to a term when read in the context of the claim, specification, and prosecution history.” Id.

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