Hazani v. United States International Trade Commission

126 F.3d 1473
CourtCourt of Appeals for the Federal Circuit
DecidedOctober 14, 1997
DocketNos. 96-1231, 96-1262, 96-1411 and 96-1415
StatusPublished
Cited by13 cases

This text of 126 F.3d 1473 (Hazani v. United States International Trade Commission) is published on Counsel Stack Legal Research, covering Court of Appeals for the Federal Circuit primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Hazani v. United States International Trade Commission, 126 F.3d 1473 (Fed. Cir. 1997).

Opinion

BRYSON, Circuit Judge.

This ease involves semiconductor memory cells. Appellants Emanuel Hazani and Patent Enforcement Fund, Inc. (collectively Hazani), petitioned for relief in the United States International Trade Commission (ITC) against a number of importers of electronic products. Hazani contended that the importers were engaged in unfair import trade practices, in violation of 19 U.S.C. § 1337, because their importation and sale of imported goods in the United States infringed Hazard’s rights under a U.S. patent relating to semiconductor memory cells. The ITC denied relief on the ground that the asserted claims of Hazani’s patent were either invalid or not infringed by the respondents. We affirm.

I

A

Semiconductor memories generally consist of a number of individual memory cells. One type of semiconductor memory is an electrically erasable programmable read-only memory (EEPROM). EEPROMs are non-volatile memories; that is, the data stored in the memory cells of an EEPROM is not lost when the power to the memory device is turned off.

An EEPROM cell includes a field-effect transistor (FET), which has a control gate, and source and drain regions formed in a substrate. In an FET, the control gate is formed above a dielectric insulator that is deposited over the area between the source and drain regions. As voltage is applied to the control gate, mobile charged particles in the substrate form a conduction channel in the region between the source and drain regions. Once the channel forms, the transistor turns “on” and current may flow between the source and drain regions.

An EEPROM may be formed by adding a “floating gate,” a conductive plate located in the dielectric insulator between the control gate and the channel region. The control gate, dielectric insulator, and floating gate form a capacitor that is capable of storing charge on the floating gate. If the floating gate is storing charge of an appropriate polarity, the FET of the EEPROM cannot turn on, thus indicating one memory state. When the floating gate is not storing any charge, the FET may operate as it does in the absence of the floating gate, which indicates the other memory state.

B

Hazani owns U.S. Patent No. 5,166,904 (the ’904 patent) entitled “EEPROM Cell Structure And Architecture With Increased Capacitance and With Programming and Erase Terminals Shared Between Several Cells.” The claims of the ’904 patent are not explicitly limited to EEPROM semiconductor memory cells, but generally relate to a semiconductor memory cell having features found in EEPROM cells.

Hazard filed a complaint with the ITC alleging that certain dynamic random access memory devices (DRAMs) imported by suppliers of electronic components infringe various claims of the ’904 patent. In early 1995, the ITC began an investigation of Hazani’s complaint, naming the importers and their American distributors as respondents.

The administrative law judge to whom the case was assigned ruled in favor of the respondents, issuing three summary dispositions, the last of which terminated the investigation. The administrative law judge ruled that all of the asserted claims except claim 14 were anticipated under 35 U.S.C. § 102(e) by U.S. Patent No. 4,758,986 to Kuo. Claim 14, the administrative law judge ruled, was not [1476]*1476infringed by any of the accused products. The ITC declined to review the summary determination orders and the order terminating the investigation.

II

On appeal, Hazani challenges all three summary determinations. The question whether a summary determination is proper is a question of law. See 19 C.F.R. § 210.18(b) (summary determination is proper “if the evidence of record show[s] that there is no genuine issue as to any material fact and that the moving party is entitled to summary determination as a matter of law”). We review summary determinations de novo. See Intellicall, Inc. v. Phonometrics, Inc., 952 F.2d 1384, 1387, 21 USPQ2d 1383, 1386 (Fed.Cir.1992). Because the administrative law judge has not made any factual determinations at this stage in the proceedings, the substantial evidence standard of review is not applicable. Contrary to the ITC’s suggestion, LaBounty Manufacturing, Inc. v. United States International Trade Commission, 867 F.2d 1572, 9 USPQ2d 1995 (Fed.Cir.1989), does not hold otherwise.

Hazani first challenges the determination that claims 1-2, 4-13, 15-17, 22, and 25 are anticipated by Kuo. Claim 1 is representative; it recites:

1. A semiconductor memory cell including a capacitor that is coupled to a field effect transistor (FET), said memory cell and said capacitor and said transistor are formed on a semiconductor substrate and wherein said capacitor is insulated from the control gate of said transistor, and said capacitor comprising:
an electrically conductive polysilicon first plate having a surface that was textured to have a predetermined pattern;
a first insulator constituting an oxide dielectric layer being disposed over and in contact with said textured surface of said polysilicon first plate;
a second insulator having at least one dielectric layer with a higher dielectric constant than the dielectric constant of said oxide layer, said second insulator being disposed along and in contact with said first insulator so that said first insulator is disposed between said first plate and said second insulator;
a second plate of an electrically conductive material being disposed along and in contact with said second insulator to form a sandwich wherein said dielectric layers are disposed between said plates, thereby said capacitor exhibiting increased capacitance and said capacitor exhibiting reduced charge transport capability between said plates so that it is lower than the charge transport capability characteristically exhibited by said first insulator alone in all modes of operation of said memory cell.

Hazani raises two main challenges to the anticipation ruling. First, Hazani argues that claim 1 requires a structure that stores charge in all modes of operation, and that the Kuo patent does not disclose such a structure. Second, Hazani argues that Kuo’s structure does not inherently satisfy the “increased capacitance” and “reduced charge transport” limitations in the “thereby” clause of claim 1.

The ITC and the respondents contend that the arguments Hazani presses upon us were not timely raised before the administrative law judge and therefore should be deemed waived.

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126 F.3d 1473, Counsel Stack Legal Research, https://law.counselstack.com/opinion/hazani-v-united-states-international-trade-commission-cafc-1997.