Fifth Generation Computer Corp. v. International Business MacHines Corp.

416 F. App'x 74
CourtCourt of Appeals for the Federal Circuit
DecidedJanuary 26, 2011
Docket2010-1201
StatusUnpublished
Cited by4 cases

This text of 416 F. App'x 74 (Fifth Generation Computer Corp. v. International Business MacHines Corp.) is published on Counsel Stack Legal Research, covering Court of Appeals for the Federal Circuit primary law. Counsel Stack provides free access to over 12 million legal documents including statutes, case law, regulations, and constitutions.

Bluebook
Fifth Generation Computer Corp. v. International Business MacHines Corp., 416 F. App'x 74 (Fed. Cir. 2011).

Opinion

LOURIE, Circuit Judge.

Fifth Generation Computer Corporation (“Fifth Generation”) appeals from the dismissal by the District Court for the Southern District of New York of its suit against International Business Machines Corporation (“IBM”) for infringement of U.S. Patent 6,000,024 (the “'024 patent”). Following the court’s claim construction, Fifth Generation Computer Corp. v. Int’l Business Machines Corp., 678 F.Supp.2d 184 *75 (S.D.N.Y.2010), the parties stipulated to noninfringement of the asserted patent claims by IBM's accused computer system. The district court entered judgment of noninfringement in favor of IBM. Because we construe at least one of the disputed terms in the same manner as the district court did, we affirm its judgment of noninfringement.

BACKGROUND

Fifth Generation owns the `024 patent directed to a binary tree parallel computing system and issued to James Maddox, Fifth Generation's chief engineer. Parallel computing systems seek to increase their speed and processing power by employing multiple computer processors that operate simultaneously. The system divides computing tasks among the several processors, thus increasing the number of computations that can be performed in a given period of time. The parallel processing system claimed in the `024 patent is one configured as a "binary tree" system. `024 patent, Abstract. Figure 1 from the `024 patent depicts an embodiment of the patented system:

[[Image here]]

In the patented computer system, a number of Processor Elements ("PE"), each comprising a processor, associated random access memory, and an input/output device, are connected with each other and with a host computer (13) over a "binary tree-bus" consisting of bus control nodes such BC1 (15), BC2 (17) and BC3 (19). `024 patent, col.2 11.28-36. As can be seen in Figure 1 of the `024 patent, each node is connected to its own PE and, depending upon the location of the node, to either two "child bus control nodes" or two "leaf PEs." Id., col.2 11.43-49 ("The nodes BC2 and BC3 are each connected to their own PE's, PE2 and PE3 respectively, and to left and right child PEs, PE4 and PE5, and PE6 and PE7, respectively..., referred to as the leaf PE's since they have no other children."). One of the bus control nodes, a "root node" (15), attaches the tree to the host through a driver (14) and a *76 PCI bus (16). '024 patent, col.2 11.50-53. The root node can receive a problem to be solved from the host computer and distribute a portion of the problem to each PE in the tree. The PEs then execute the system’s instructions, ie., perform the necessary calculations, and pass their solutions back up the tree toward the root node, which determines the overall solution to the problem it received from the host computer. The input/output device in each PE functions to transmit data up and down the tree levels. Claim 1 is representative of the patented parallel computing system:

1. A binary tree computer system for connection to and control by a host computer, comprising:

N bus controllers connected in a binary tree configuration in which each bus controller, except those at the extremes of the tree, are connected to left and right child bus controllers, where N is an integer greater than 2, one of said bus controllers being a root bus controller for connecting said binary tree connected bus controllers to said host computer;
N processing elements, one attached to each of said bus controllers;
N -I-1 leaf processing elements connected, two each, as right and left children to the bus controllers at the extremes of said binary tree;
each of said processing elements including a microprocessor and a memory;
each of said bus controllers including, for each processing element connected thereto, a buffered interface connecting said processing element to said bus controller for transmitting instructions and data between the bus controller and the connected processing element, and means for writing information into the memory of the connected processing element without involving the microprocessor of said connected processing element.
'024 patent, claim 1 (emphases added).

The only other independent claim of the '024 patent, claim 7, recites a similar system. The '024 patent cites as prior art and incorporates by reference two other patents that are also assigned to Fifth Generation, U.S. Patents 4,843,540 and 4,860,201 to Salvatore Stolfo and Daniel Miranker (the “'540 and '201 patents” or the “Stolfo patents”). Those patents also claim a binary tree computer system as depicted by Figure 2 in the '201 patent:

*77 [[Image here]]

The `201 patent specification explains that the binary tree processing system is partitionable "into a number of subtrees which maintain the full functionality of the ordinal tree." `201 patent, col.10 11.53-55. The `540 patent similarly illustrates the concept of a binary tree being comprised of sub-binary trees. `540 patent, col.6 11. 8-15 ("When functioning independent of its parent element the data processing element can act as a root element for a sub-binary tree formed by the lower order data processing elements connected below it.").

In October 2008, Fifth Generation brought suit against IBM in the United States District Court for the Eastern District of Texas, alleging infringement of the `024, `540 and `201 patents by IBM's Blue Gene supercomputer, which is a large scale parallel computing system. In March 2009, the case was transferred to the Southern District of New York, following which Fifth Generation, by joint motion, dropped claims of infringement of the `540 patent. The court construed claims of the `024 and `201 patents in August 2009, as a result of which Fifth Generation conceded that it could not prove infringement of the asserted claims by IBM's system under the district court's construction of at least one claim limitation, the "root bus controller."

On January 6, 2010, the court issued a detailed claim construction opinion, Fifth Generation, 678 F.Supp.2d 184, and subsequently entered final judgment of noninfringement against Fifth Generation. J.A.1. The court held that the "root bus controller," as used in the `024 claims, connects the binary tree of bus controllers to the host computer. Fifth Generation, 678 F.Supp.2d at 201. The court read the claims to mean that the root bus controller is necessarily the link between the binary tree of bus controllers and the host computer. Id. at 202. The court reasoned that, as such, the root bus controller is the highest order bus controller and can have no parent bus controllers. Id. Thus, the court construed the term to mean "the bus controller at the highest order position of the binary tree computer system that connects the binary tree to the host computer and which has no parent bus controller." Id. In so holding, the court rejected Fifth *78

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416 F. App'x 74, Counsel Stack Legal Research, https://law.counselstack.com/opinion/fifth-generation-computer-corp-v-international-business-machines-corp-cafc-2011.