1 2 3 4 UNITED STATES DISTRICT COURT 5 NORTHERN DISTRICT OF CALIFORNIA 6 7 ALPHA AND OMEGA Case No. 22-cv-05448-PCP SEMICONDUCTOR LIMITED, et al., 8 Plaintiffs, ORDER DENYING MOTION TO 9 STRIKE v. 10 Dkt. No. 59 FORCE MOS TECHNOLOGY CO., LTD., 11 Defendant.
12 13 Defendant Force MOS Technology Co., Ltd. has moved to strike plaintiffs’ patent 14 infringement contentions, filed pursuant to Patent Local Rules 3-1 and 3-2. For the reasons set 15 forth below, the Court upon review concludes that each of the infringement contentions at issue is 16 sufficient to provide reasonable notice to Force MOS. The motion is therefore denied. 17 I. Background 18 This is a patent case involving metal oxide semiconductor field effect transistors, or 19 MOSFETs. The parties have filed several rounds of pleadings. As the case now stands, seven 20 patents are at issue. Force MOS claims that plaintiffs Alpha and Omega Semiconductor Limited 21 and Alpha and Omega Semiconductor Inc. (AOS) have infringed three of its U.S. patents, 22 numbered 7,629,634; 7,847,346; and 7,646,058. AOS, in turn, claims that Force MOS has 23 infringed four of AOS’s patents, numbers 8,067,304; 7,511,361; 7,781,265; and 8,928,079. The 24 parties also variously claim invalidity and seek declaratory judgments of non-infringement. 25 Pursuant to Patent Local Rules 3-1 and 3-2, AOS served its “Disclosure of Asserted Patent 26 Claims and Infringement Contentions” as to its ’304, ’361, and ’265 patents on January 31, 2023, 27 and served supplemental infringement contentions as to its ’079 patent on April 14, 2023. Force 1 to resolve this dispute on their own, Force MOS filed this motion. Force MOS asks the Court to 2 || strike AOS’s infringement contentions as to several of the claims of AOS’s and ’079 patents. 3 MOSFETs are semiconductor chips. The fabrication process begins with a wafer, a thin 4 || disc of semiconductive material that can be used to produce many individual chips. AOS’s □□□□ 5 patent involves a method for forming a layer of metal 3-6 microns thick on the top surface of a 6 || wafer that has built-in “alignment marks.” Alignment marks are indentations at specified locations 7 around the wafer which are used to line up a mask for a later step in the fabrication process. But 8 adding a layer of metal on top of the wafer can degrade the sharpness of the alignment marks, 9 which in turn makes alignment for the masking process less precise—a problem as manufacturers 10 || aim to make chips smaller and smaller. Using “hot” metal (400° C) to create this layer is 11 beneficial in some ways because hot metal has good “step coverage,” or in other words, is better 12 || than “cold” metal (300° + 50° C) at filling in voids in the surface of the wafer. But this same 5 13 property means that using hot metal can degrade the sharpness of the alignment marks. Figure 1D 14 || from the ’304 patent shows a cross section of an alignment mark before the metal layer is added, 3 15 and Figure 2B illustrates how the alignment mark can be degraded when a layer of metal is added: 16
20 21 Fig. 1D Fig. 2B 22 23 || The gist of the ’304 patent is that by adding two metallization layers—a thin hot one followed by a 24 || thicker cold one—instead of a single thick layer (as illustrated in Figure 2B), the beneficial 25 || properties of the hot layer’s contact with the surface of the wafer can be taken advantage of while 26 || better preserving the sharpness of the alignment mark. Figure 3B illustrates the difference: 27 28
5 Fig. 2B Fig. 3B 6 7 There are some inherent tradeoffs between certain characteristics of MOSFETs, and 8 || depending on the intended application manufactures can seek to strike a different balance. One 9 such characteristic is the resistance between the transistor’s “source” and “drain” terminals when it 10 || is “on,” or in other words, when a voltage is applied to the “gate” terminal. This resistance value is 11 referred to as Rpgcon) Or the on-resistance. A MOSFET’s on-resistance is typically proportional to 12 || the length of the channel between the source and drain terminals and inversely proportional to the 13 concentration of individual cells in the chip. The MOSFET’s gate capacitance is proportional to 14 |) both channel length and cell concentration. If the goal is to minimize on-resistance, two options 2 15 are to reduce channel length or increase cell concentration. But cell concentration is limited by the 16 || current state of manufacturing technology, and channel length is limited by what is known as the 2 17 “punch-through” phenomenon. AOS’s ’079 patent outlines a MOSFET manufacturing process that Z 18 aims to address some of these tradeoffs and reduce both the on-resistance and gate capacitance. 19 || II. — Legal Standard 20 Patent Local Rule 3-1 requires a party alleging patent infringement to serve a “Disclosure 21 of Asserted Claims and Infringement Contentions.” The infringement contentions must, for each 22 || claim allegedly infringed, identify “each accused apparatus, product, device, process, method, act, 23 or other instrumentality.” Next, for each accused instrumentality, the claimant must provide a 24 || “chart identifying specifically where and how each limitation of each asserted claim is found.” 25 Rule 3-1 is essentially a discovery shortcut: It “takes the place of a series of interrogatories 26 || that defendants would likely have propounded had the patent local rules not provided for 27 streamlined discovery.” Network Caching Tech. LLC v. Novell, Inc., No. 01-cv-02079-VRW, 28 2002 WL 32126128, at *4 (N.D. Cal. Aug. 13, 2002). “These rules require parties to crystallize
1 their theories of the case early in litigation,” and they “provide structure to discovery” to enable 2 efficient resolution of the dispute. Creagri, Inc. v. Pinnaclife Inc., LLC, No. 11-CV-06635-LHK- 3 PSG, 2012 WL 5389775, at *2 (N.D. Cal. Nov. 2, 2012) (cleaned up). The rules do not “require 4 the disclosure of specific evidence nor do they require a plaintiff to prove its infringement case.” 5 Id. Instead, “to the extent appropriate information is reasonably available,” the rules require the 6 plaintiff “to disclose the elements in each accused instrumentality that it contends practices each 7 and every limitation of each asserted claim” Id. The minimum standard is that “the degree of 8 specificity under Local Rule 3-1 must be sufficient to provide reasonable notice to the defendant 9 why the plaintiff believes it has a reasonable chance of proving infringement,” and the contentions 10 “must map specific elements of Defendants’ alleged infringing products onto the Plaintiff’s claim 11 construction.” Shared Memory Graphics LLC v. Apple, Inc., 812 F. Supp. 2d 1022, 1025 (N.D. 12 Cal. 2010) (cleaned up). 13 “Where appropriate, courts treat a motion to strike as a motion to compel amendment to 14 include additional information.” France Telecom, S.A. v. Marvell Semiconductor, Inc., No. 12- 15 CV-04967-WHA-NC, 2013 WL 1878912, at *2 (N.D. Cal. May 3, 2013). 16 III. Analysis 17 Force MOS argues that several of AOS’s infringement contentions are deficient. The 18 contentions at issue are addressed in turn below. For the reasons set forth, the Court concludes that 19 all of these contentions provide adequate notice and are sufficient under Patent Local Rule 3-1. 20 A. The ’304 Patent 21 1. Claim 4 22 Claim 4 of the ’304 patent states:
23 The power semiconductor device of claim 1 wherein said first metal 24 layer comprising a hot metallization layer in the bottom and a cold metallization layer on the top. 25 26 Dkt. No. 59-2, at 32. AOS provides the following infringement contention for this claim with 27 respect to Force MOS’s MEE7816AS-G device: 1 claim 1 above. 2 The MEE7816AS-G’s first metal layer comprising a hot metallization layer in the bottom and a cold metallization layer on the top. See, e.g., 3 The cross-sectional image of the MEE7816AS-G below shows the 4 first metal layer. On information and belief, the first metal layer 5 comprises a hot metallization layer in the bottom and a cold metallization layer on the top. 6 7
9 | — oe or ede A re. = oe ee i= ft 2 4 10 ee le rin iy □□ wae | oe ll □□ UU UU wy a Na Rx: rf “a | ; a 12 ee ee 7 rs a ener 2B
15 |} Id. at 32-33. 16 Force MOS argues that this contention is deficient because AOS makes a “conclusory
= 17 assertion that ‘on information and belief? that [sic] this ‘First metal layer’ satisfies the hot
18 || metalization [sic] layer in the bottom and cold metallization layer on the top as additionally 19 || required of Claim 4” but fails to provide any “supporting commentary, analysis, images, 20 additional evidence, or even mere identification to show how the first metal layer is [sic] 21 comprises either a hot metalization layer or, a cold metalization, or and certainly not both 22 || simultaneously.” Dkt. No. 59, at 10. Force MOS argues that AOS “merely provides improper 23 ‘information and belief? and an unhelpful image that does not even attempt to identify ‘a hot 24 || metallization layer’ nor ‘a cold metallization layer,’” and “leaves Force MOS to guess where AOS 25 contends the cold and hot metallization layers are.” Id. 26 AOS counters that there is “nothing confusing” about its Claim 4 contentions and 27 emphasizes that in addition to the image of the accused product, AOS has also included both a 28 label and explanation. Dkt. No. 68, at 10.
1 This infringement contention is sufficient under Patent L.R. 3-1. AOS is not required to 2 prove infringement at this stage, or to provide commentary, analysis, or evidence. AOS is simply 3 required to provide reasonable notice to Force MOS as to why, based on the information available 4 to AOS, it thinks it has reasonable chance of proving infringement. In context, AOS’s assertion 5 that the “first metal layer” identified in the accompanying image “comprises a hot metallization 6 layer in the bottom and a cold metallization layer on the top” provides adequate notice. Force 7 MOS is correct that AOS includes the phrase “on information and belief” in this contention, but 8 AOS has gone beyond simply concluding based on information and belief that the accused product 9 infringes the claim, or parroting the language of the claim without any further explanation or 10 context. No great mental leap is required to deduce from the image which side of the identified 11 first metal layer is the “top” and which is the “bottom,” as Force MOS seems to fault AOS for 12 failing to clarify. The Court will not strike this contention. 13 Force MOS argues that AOS’s contentions for Force MOS’s ME4435-G device, Dkt. No. 14 59-2, at 65, are essentially identical to its contentions for the MEE7816AS-G device. These 15 contentions are sufficient for the same reasons. 16 2. Claim 5 17 Claim 5 states:
18 The power semiconductor chip of claim 4 wherein said hot 19 metallization layer has a thickness between 0.5-1 micron. 20 Dkt. No. 59-2, at 33. AOS provides the following infringement contention for this claim with 21 respect to Force MOS’s MEE7816AS-G device:
22 The MEE7816AS-G is a power semiconductor device of claim 4. See 23 claim 4 above.
24 The MEE7816AS-G’s hot metallization layer has a thickness between 0.5-1 micron. 25 For example, on information and belief, the MEE7816AS-G’s hot 26 metallization layer has a thickness between 0.5-1 micron, as a result 27 o f Force MOS’s MOSFET manufacturing processes. 1 Force MOS argues that these contentions are deficient because they are “essentially 2 identical” to the language of the claim, and AOS “does not even provide an image or any other 3 evidentiary citation.” Dkt. No. 59, at 11. In response, AOS emphasizes that it is not required to 4 disclose specific evidence or prove its infringement case at this stage. Dkt. No. 68, at 11. 5 Force MOS is correct that courts in other cases have sometimes found infringement 6 contentions that simply repeat claim language to be insufficient. But the ultimate inquiry is still 7 whether the contentions provide reasonable notice of why a plaintiff thinks a defendant’s products 8 may infringe. Here, Claim 5 is extremely straightforward. All it adds to Claim 4 is the specific 9 dimension of one element: the hot metallization layer. Indeed, given the simplicity of this claim, it 10 is hard to imagine how infringement could be alleged without to some extent parroting the 11 language or at least the essential structure of the claim. In addition, Claim 5 is tied to Claim 4, and 12 AOS’s infringement contentions for Claim 5 refer back to its contentions for Claim 4, including 13 the image it included. Taken in context, AOS’s contentions are clear enough to provide adequate 14 notice. Requiring AOS to reinclude the image from its Claim 4 contention in its Claim 5 15 contention as a matter of box-checking would not be useful and would not further the purposes of 16 Patent L.R. 3-1. These contentions suffice and will not be stricken. 17 3. Claim 7 18 Claim 7 states:
19 The power semiconductor chip of claim 4 wherein a ratio of the cold 20 metallization thickness to hot metallization thickness ranges from about 3:1 to about 7:1. 21 22 Dkt. No. 59-2, at 34. AOS provides the following infringement contention for this claim with 23 respect to Force MOS’s MEE7816AS-G device:
24 The MEE7816AS-G is a power semiconductor device of claim 4. See claim 4 above. 25
26 In the MEE7816AS-G, a ratio of the cold metallization thickness to hot metallization thickness ranges from about 3:1 to about 7:1. 27 For example, on information and belief, the ratio of the MEE7816AS- from about 3:1 to about 7:1, as a result of Force MOS’s MOSFET 1 manufacturing processes. 2 Id. AOS’s contentions for the Force MOS ME4435-G device are similar. See id. at 66. 3 As with Claim 5, although AOS’s infringement contention does parallel the language of 4 the claim, the simplicity of the claims makes this inevitable and the contention is sufficient to 5 provide notice to Force MOS, especially since this claim is dependent. Force MOS faults AOS for 6 failing to indicate “what aspect of the manufacturing process causes this limitation to be satisfied” 7 or specifying “where or how AUS is measuring the thickness of the respective layers.” Dkt. No. 8 59, at 12. That level of specificity is not required at this stage. AOS contends that the accused 9 product has cold and hot metallization layers whose thicknesses satisfy the ratio set out in the 10 claim. AOS does not need to know or specify how that ratio is manufactured in order to contend 11 that it occurs. These contentions are also sufficient and will not be stricken. 12 4. Claim 10 13 Claim 10 states:
14 The power semiconductor chip of claim 9 further comprising:
15 10[a]: a second metal layer overlaying the dielectric layer contacting the insulated gate through the gate contact openings, and 16
17 10[b]: said second metal layer further comprising a hot metallization layer at the bottom and a cold metallization layer on the top. 18 19 Dkt. No. 59-2, at 37. AOS provides the following infringement contentions for these claims with 20 respect to Force MOS’s MEE7816AS-G device:
21 The MEE7816AS-G power semiconductor chip of claim 9. See claim 9. 22
23 The MEE7816AS-G includes a second metal layer overlaying the dielectric layer contacting the insulated gate through the gate contact 24 openings. See limitation 2[b].
25 The MEE7816AS-G’s second metal layer comprises a hot metallization layer at the bottom and a cold metallization layer on the 26 top. 27 For example, when manufacturing MOSFETs, it is common to use a second metal layer. On information and belief, this is true for the 1 MEE7816AS-G. Thus, the analysis for the “first metal layer” for 2 c laim 4 also applies for this limitation. See claim 4. 3 Id. AOS’s contentions for Force MOS’s ME4435-G device are similar. See id. at 69–70. 4 Force MOS argues that this contention, which ties back to the contention for Claim 4, is 5 deficient for similar reasons. Force MOS also faults AOS for basing this contention on its 6 understanding of “common” practices without providing any “documentation or citation to 7 evidence.” Dkt. No. 59, at 13. As explained above, however, AOS’s infringement contention for 8 Claim 4 is sufficient under the Local Rules. This contention is as well. Documentation and 9 evidence, while helpful if available, are not required. 10 5. Claim 11 11 Claim 11 states:
12 The power semiconductor chip of claim 10 wherein said hot 13 m etallization layer has a thickness between 0.5-1 micron. 14 Dkt. No. 59-2, at 37. AOS provides the following infringement contention for this claim with 15 respect to Force MOS’s MEE7816AS-G device:
16 The MEE7816AS-G is a power semiconductor device of claim 10. 17 See claim 10 above.
18 The MEE7816AS-G’s hot metallization layer has a thickness between 0.5-1 micron. 19 For example, when manufacturing MOSFETs, it is common to use a 20 substantially similar process to form both the first metal layer and the 21 second metal layer. On information and belief, this is true for the MEE7816AS-G. Thus, the analysis for the “hot metallization layer” 22 for claim 5 also applies for this claim. See claim 5.
23 24 Id. AOS’s contentions for the Force MOS ME4435-G device are similar. See id. at 70. 25 This claim largely parallels Claim 5 except that it applies to the hot metallization layer of 26 the second metal layer rather than the first metal layer. AOS’s Claim 11 infringement contentions 27 are sufficient for the same reasons its Claim 5 contentions are. 1 6. Claim 13 2 Claim 13 states:
3 The power semiconductor chip of claim 10 wherein a ratio of the cold 4 metallization thickness to hot metallization thickness ranges from about 3:1 to about 7:1. 5 6 Dkt. No. 59-2, at 38. AOS provides the following infringement contention for this claim with 7 respect to Force MOS’s MEE7816AS-G device:
8 The MEE7816AS-G is a power semiconductor device of claim 10. 9 See claim 10 above.
10 In the MEE7816AS-G, a ratio of the cold metallization thickness to hot metallization thickness ranges from about 3:1 to about 7:1. 11
12 For example, when manufacturing MOSFETs, it is common to use a substantially similar process to form both the first metal layer and the 13 second metal layer. On information and belief, this is true for the MEE7816AS-G. Thus, the analysis for the “hot metallization layer” 14 and the “cold metallization layer” for claim 7 also applies for this claim. See claim 7. 15 16 Id. AOS’s contentions for the Force MOS ME4435-G device are similar. See id. at 70–71. 17 This claim largely parallels Claim 7. AOS’s Claim 13 contentions are sufficient for the 18 same reasons its Claim 7 contentions are. 19 7. Claim 14 20 Claim 14 states:
21 The power semiconductor chip of claim 10 wherein said second metal 22 layer has a top surface of step profile substantially conforming to a topography of its underlying dielectric layer. 23 24 Dkt. No. 59-2, at 38. AOS provides the following infringement contention for this claim with 25 respect to Force MOS’s MEE7816AS-G device:
26 The MEE7816AS-G is a power semiconductor device of claim 10. See claim 10 above. 27 1 profile substantially conforming to a topography of its underlying dielectric layer. See, e.g., 2 As shown in the optical microscopic image below, the MEE7816AS- 3 G’s second metal layer has a top surface of step profile substantially conforming to a topography of its underlying dielectric layer. 4 5 6
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12 is a 14 15 || Id. at 38-39. AOS’s contentions for Force MOS’s ME4435-G device are similar. See id. at 71-72. Qa 16 Force MOS argues that AOS’s contentions for Claim 14 are deficient for the same reasons
= 17 as its Claim 13 contentions. Force MOS faults AOS for basing its contentions on “common”
18 techniques and asserting infringement based on “information and belief.” Dkt. No. 59, at 15. 19 AOS’s contention for Claim 14 does not use these terms, however, as shown above. It is possible 20 || this argument may have been intended for another of AOS’s contentions. Regardless, the Claim 14 21 contentions are sufficient. 22 B. The ’079 Patent 23 1. Claims 8 and 18 24 Claim 8 of the ’079 patent states: 25 The semiconductor device of claim 1, further comprising an anti- 6 punch through implant disposed on a sidewall of the active region contact trench. 27 28 Dkt. No. 59-3, at 38-39. AOS provides the following infringement contention for this claim with
1 respect to Force MOS’s ME2N70026D2KW device: 2 The ME2N70026D2KW includes the semiconductor device of claim 3 1. See claim | above. 4 The ME2N70026D2KW includes an anti-punch through implant disposed on a sidewall of the active region contact trench. See, e.g., 5 The following SEM image of ME2N70026D2KW shows the 6 E2N70026D2KW active region contact trench. On information and 4 belief, the ME2N70026D2KW has an anti-punch through implant disposed on a sidewall of the active region contact trench. 8 9 10
12 £ |
13 Contact Gate trench
= 17 S Ca ry re) eee 18 a ei] nny eee A Re eee la 0 Oa ss 19 || Id. at 38-39. AOS’s contentions for Force MOS’s ME4435 device are similar. See id. at 79-80. 20 According to Force MOS, AOS’s contentions are insufficient because AOS simply points 21 to the location of a sidewall on an image and asserts “on information and belief” that the accused 22 || product has an anti-punch through implant disposed on the sidewall. See Dkt. No. 59, at 16. Force 23 MOS argues that the image does not actually show the anti-punch through implant, that the sides 24 || of the contact trench do not appear visually distinct from other areas of the contact trench in the 25 image, and that Force MOS has no way of knowing what parts of its manufacturing process AOS 26 || contends generate those implants. Jd. AOS counters that its contentions are clear, and that because 27 Claim 8 is an apparatus claim, it does not need to identify the parts of Force MOS’s manufacturing 28 || process that could generate such an implant.
1 AOS’s Claim 8 contentions are adequate. The annotated image that AOS has provided is 2 clear enough to provide reasonable notice. Even if the anti-punch through implants do not appear 3 visually distinct in the image standing alone, AOS has supplemented the image by pointing out 4 specifically where it believes the implants are located. That is clear enough. The case Force MOS 5 relies on does not support its argument. In Infineon Technologies AG v. Volterra Semiconductor 6 Corp., the plaintiffs “reference[d] a birds-eye image” of an accused product asserted as “show[ing] 7 a metal layer,” but the Court concluded that the image did “not allow the viewer to discern 8 whether [it] depicts one or multiple layers, let alone which specific layer(s) are shown,” and that 9 the “Defendant … is entitled to know which layer or layers allegedly infringe.” No. 11-cv-06239- 10 MMC-DMR, 2013 WL 322570, at *3 (N.D. Cal. Jan. 28, 2013). Here, even if the image alone 11 might not be clear enough to enable Force MOS to discern which portions showed the alleged 12 infringement, AOS has done exactly what Infineon suggests is required by clearly annotating and 13 labeling the image. These contentions are sufficient and will not be stricken. 14 Force MOS argues that the same analysis applies to Claim 18 because AUS replies on its 15 Claim 8 contentions. Because the Court concludes that the Claim 8 contentions are sufficient, the 16 Claim 18 contentions are similarly acceptable. 17 2. Claims 9 and 19 18 Claim 9 states:
19 The semiconductor device of claim 1, further comprising a blanket 20 implant deposited throughout the epitaxial layer, wherein the blanket implant has opposite polarity as the epitaxial layer. 21 22 Dkt. No. 59-3, at 39–40. AOS provides the following infringement contention for this claim with 23 respect to Force MOS’s ME2N70026D2KW device:
24 The ME2N70026D2KW includes the semiconductor device of claim 1. See claim 1 above. 25
26 The ME2N70026D2KW includes a blanket implant deposited throughout the epitaxial layer, wherein the blanket implant has 27 opposite polarity as the epitaxial layer. See, e.g., 1 ME2N70026D2KW epitaxial layer. On information and belief, the ME2N70026D2KW has a blanket implant deposited throughout the 2 epitaxial layer. On information and belief, the blanket implant has opposite polarity as the epitaxial layer. 3 4 5 6 7 i eg g Te st} be i en Pt it Layer of body region 9 0 11 . Blanket implant 12
2B ae Eerie a a Roe an i Ee ee
15 16 || Id. at 39-40. AOS’s contentions for the Force MOS ME4435-G device are similar. See id. at 81.
= 17 Force MOS argues that AOS’s contentions are “not based on an analysis of the Force MOS
18 product,” but rather merely an “information and belief” guess. Force MOS also complains that the 19 || arrow labeling the “blanket implant” does not point to any identifiable structure and the various 20 || regions in the image are “visually indistinct.” Dkt. No. 59, at 18-19. 21 AOS’s contentions are again sufficient. Here, as with Claim 8, the image alone might be 22 || insufficient for the reasons that Force MOS has pointed out: It is difficult to tell without more 23 where the various alleged regions are delineated. But AOS has provided more, in the form of a 24 || dotted line showing where the blanket implant is asserted to be and labels indicating the regions 25 on either side. This is clear enough in context to provide reasonable notice to Force MOS. Force 26 || MOS seems to want a better image that clearly depicts the various regions of its product. But that 27 is the kind of evidentiary showing that is not required at this stage by Patent Rule 3-1. These 28 contentions are adequate and will not be stricken.
1 As with Claim 18, AOS’s contentions for Claim 19 refer back to Claim 9. The limitation 2 || added to Claim 13 by Claim 19 is similar to the limitation added to Claim 1 by Claim 9. The 3 Claim 19 contentions are therefore acceptable for the same reasons the Claim 9 contentions are. 4 3. Claims 10 and 20 5 Claim 10 states: 6 The semiconductor device of claim 1, further comprising an epitaxial 7 layer profile tuning implant deposited under the active region contact trench. 8 9 Dkt. No. 59-3, at 40-41. AOS provides the following infringement contention for this claim with 10 || respect to the Force MOS ME2N70026D2KW device: 11 The ME2N70026D2KW includes the semiconductor device of claim 1. See claim | above. 12
& 13 The ME2N70026D2KW includes an epitaxial layer profile tuning implant deposited under the active region contact trench. See, e.g.,
S The following SEM image of ME2N70026D2KW shows the 15 E2N70026D2KW active region contact trench and epitaxial layer. On A 16 information and belief, the ME2N70026D2KW has an epitaxial layer profile tuning implant deposited under the active region contact 3 17 trench.
contact trench 19 | | | 21
tuning implant 24
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1 Id. AOS’s contentions for Force MOS’s ME4435-G device are similar. See id. at 81-82. 2 Force MOS again faults AOS for including assertions on “information and belief” without 3 additional support, arguing that AOS merely “guesses” that the indicated region includes the 4 || epitaxial layer profiling tuning implant even though the region is not visually distinct in the image. 5 || But again, AOS has done all that is required here. Whether AOS is correct in its belief is a 6 || question for later in the case. But what AOS believes with respect to infringement of this claim is 7 clear enough to provide notice to Force MOS. These contentions will not be stricken. 8 AOS’s contentions for Claim 20 refer back to Claim 10. And the limitation added to Claim 9 13 by Claim 20 is similar to the limitation added to Claim | by Claim 10. The Claim 20 10 |) contentions are acceptable for the same reasons the Claim 10 contentions are. 11 4. Claims 12 and 22 a 12 Claim 12 states:
413 The semiconductor device of claim 1, wherein the body and the 14 semiconductor substrate have opposite polarities.
15 || Dkt. No. 59-3, at 42. AOS provides the following infringement contention for this claim with
Q 16 || respect to the Force MOS ME2N70026D2KW device:
vo M7 The ME2N70026D2KW includes the semiconductor device of claim 12 1. See claim 1 above. 19 The ME2N70026D2KW includes the body and the semiconductor substrate have opposite polarities. See, e.g., 20 4 As shown in the datasheet below, ME2N70026D2KW is a dual N- Channel MOSFET. 22 Force mos Motsuki Electric ME2N70026D2KW-.G 23 Dual N - Channel 60V (D-S) MOSFET, ESD Protection GENERAL DESCRIPTION FEATURES 24 The ME2N7002802KW-G is the Dual N-Channel logic enhancement @ Rosomsaogves=wVv n it if field effect transistors are produced using high cell Rosow 40 Vas=4.5¥ moce powe! . ge : Rosin <4 over 5 density, DMOS trenen technology. This high densily process is @ ESD Protwetion HEM 5210 eapedally tailored to minimize on-state resistance. These devices © Super high deneity cal design for extremely low Roson @re particularly suited for low vollage application such as cellular Exceptional on-resistance and maximum OC current 26 Phone and motebook computer power Management snd other battery ° capability powered em ts , and low in-line power loss are needed in a very APPLIC ATIONS 27 small outline surface mount package @ Power Management in Note book PIN CONFIGURATION Soc 28 (SOT-263) @ LCD Display inverter
| Ex. GG to AOS’s Second Amended Complaint. 2 On information and belief, ME2N70026D2KW’s semiconductor 3 substrate is N-type and its body is P-type. 4 The following SEM image of ME2N70026D2KW shows the body 5 and the semiconductor substrate. On information and belief, the semiconductor substrate and body have opposite polarities. 6 7 8 9 10 12 Contact — = bottom
Q 16 2 17 a ek wae eee ae el = Z 18 || Id. at 42-44. AOS’s contentions for Force MOS’s ME4435-G device are similar. See id. at 83-85. 19 Force MOS again faults AOS for asserting the polarities of the P-type body and N-type 20 substrate on “information and belief.” But here, as before, AOS’s assertions are more than clear 21 enough to explain its infringement contentions and provide notice to Force MOS. No further 22 || “supporting discussion or analysis” is required to support AOS’s contentions at this stage. See 23 Dkt. No. 59, at 23. These contentions are sufficient and will not be stricken. 24 AOS’s contentions for Claim 22 refer back to Claim 12. And the limitation added to Claim 25 13 by Claim 22 is similar to the limitation added to Claim | by Claim 12. The Claim 22 26 || contentions are acceptable for the same reasons the Claim 12 contentions are. 27 28
1 5. Claim 21 2 Claim 21 states: 3 The method of claim 13, further comprising: forming 4 a hard mask on the substrate prior to forming the gate trench; 5 removing a hard mask to leave a gate structure that extends above the 6 body top surface. 7 Dkt. No. 59-3, at 48-49. AOS provides the following infringement contention for this claim with 8 || respect to the Force MOS ME2N70026D2KW device: 9 The ME2N70026D2KW is manufactured using the method of claim 10 3, further comprising forming a hard mask on the substrate prior to forming the gate trench. See claim 13 above. 11 See, €.2., (12 The following SEM image of ME2N70026D2KW shows. that = 13 ME2N70026D2KW has a gate trench and substrate. On information 14 and belief, the ME2N70026D2KW is manufactured by forming a hard mask on the substrate prior to forming the gate trench. 15 16
Z 18 □
20 21 22 23 24 he Pars rag) Hs a ine a pil 7 ae ee a 25 || Id. at 42-44. AOS’s contentions for Force MOS’s ME4435-G device are similar. See id. at 91-92. 26 Force MOS argues that AOS does not provide adequate support for its contention that the 27 accused products are manufactured by forming a hard mask on the substrate prior to forming the 28 gate trench. Force MOS also argues that the included image does not disclose the relevant steps
1 and structures of its manufacturing process. 2 As AOS points out, this contention is distinct from all of the others at issue in this motion, 3 because it involves a step in the production process of the device rather than an aspect of the final 4 || product. As a result, the “precise masking information is solely in the possession of Force MOS.” 5 Dkt. No. 68, at 13. AOS argues that it has supplied all of the information it has at this point, and 6 || that this suffices under the standard set out in Creagri that disclosures are only required “to the 7 extent appropriate information is reasonably available.” Dkt. No. 68, at 13 (citing Creagri, 2012 8 || WL 5389775, at *3); see also France Telecom, 2013 WL 1878912, at *4 (ruling that plaintiff 9 “must identify how ... products infringe with as much specificity as possible with the information 10 || currently available to it” (cleaned up)). Force MOS asserts that its request to strike this contention 11 is consistent with France Telecom because AOS has allegedly provided “‘no substantive 12 || disclosure.” Dkt. No. 69, at 15. But Force MOS does not suggest that there is any other 5 13 information that is (or should be) currently available to AOS about Force MOS’s manufacturing 14 || processes on which AOS could base its contentions. 3 15 AOS’s contention is clearly insufficient to establish that Force MOS’s manufacturing 16 || process actually does infringe. But that is not required in an infringement contention. AOS has 3 17 provided adequate notice of its theory of infringement, and it is hard to see what further detail it 18 could have provided at this stage in the litigation about Force MOS’s proprietary processes. These 19 || contentions are sufficient and may remain. 20 || IV. Conclusion 21 For the reasons set forth above, Force MOS’s motion to strike is denied. 22 23 IT IS SO ORDERED. 24 Dated: December 13, 2023 25 Cy Za 26 . P. Casey Pitts United States District Judge 28